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2023-03-28 - 07:35

x86 Intel Core i5-8365UE @1600 MHz, Linux 5.10.47-rt46 (Profile)

Latency plot of system in rack #8, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack8slot4.osadl.org (updated Tue Mar 28, 2023 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2878702233176,19sleep30-21swapper/319:06:403
2880832232197,24sleep00-21swapper/019:09:420
2879852229176,19sleep60-21swapper/619:08:196
2880022222188,22sleep50-21swapper/519:08:345
2878272222188,23sleep70-21swapper/719:06:037
2879802221188,22sleep10-21swapper/119:08:151
2878152221193,18sleep40-21swapper/419:05:534
2879812219185,22sleep20-21swapper/219:08:162
28835699650,62cyclictest0-21swapper/500:24:035
3759232490,0sleep20-21swapper/221:25:152
3484592490,0sleep00-21swapper/020:50:220
5586492470,0sleep20-21swapper/200:05:222
288360994747,0cyclictest0-21swapper/623:37:516
4426872460,0sleep70-21swapper/722:25:197
4419062440,0sleep40-21swapper/422:25:164
288340994239,3cyclictest0-21swapper/000:24:020
288350993938,1cyclictest0-21swapper/300:24:033
288345993838,0cyclictest0-21swapper/222:09:242
28834299330,33cyclictest0-21swapper/122:23:321
28834099330,33cyclictest0-21swapper/021:15:010
28834099330,32cyclictest391718-21idleruntime-cro21:40:010
28835699320,31cyclictest0-21swapper/521:14:475
28835699320,28cyclictest0-21swapper/522:48:245
288345993228,1cyclictest151rcu_preempt23:00:222
28834099320,3cyclictest0-21swapper/022:21:480
28834099320,32cyclictest0-21swapper/022:59:340
28834099320,32cyclictest0-21swapper/022:11:150
28834099320,31cyclictest470156-21perf22:49:590
288360993131,0cyclictest0-21swapper/621:10:566
288356993127,4cyclictest0-21swapper/500:25:135
28835699310,31cyclictest0-21swapper/523:34:025
28835699310,31cyclictest0-21swapper/522:37:475
28835699310,30cyclictest357510-21diskmemload21:34:285
28835699310,28cyclictest0-21swapper/521:50:195
28835699310,1cyclictest357510-21diskmemload23:46:445
28835699310,0cyclictest0-21swapper/523:52:235
28835699310,0cyclictest0-21swapper/523:16:405
28835699310,0cyclictest0-21swapper/523:16:405
28835699310,0cyclictest0-21swapper/500:30:375
28835099310,30cyclictest357510-21diskmemload21:35:083
28835099310,30cyclictest0-21swapper/322:21:373
288342993131,0cyclictest0-21swapper/121:39:241
288340993127,4cyclictest0-21swapper/022:50:000
28834099310,31cyclictest0-21swapper/023:59:590
28834099310,31cyclictest0-21swapper/023:17:240
28834099310,31cyclictest0-21swapper/023:17:240
28834099310,31cyclictest0-21swapper/023:11:020
28834099310,31cyclictest0-21swapper/023:01:230
28834099310,31cyclictest0-21swapper/022:44:310
28834099310,31cyclictest0-21swapper/022:28:270
28834099310,31cyclictest0-21swapper/022:17:180
28834099310,31cyclictest0-21swapper/021:51:330
28834099310,31cyclictest0-21swapper/021:20:520
28834099310,31cyclictest0-21swapper/021:16:020
28834099310,31cyclictest0-21swapper/000:00:040
28834099310,30cyclictest0-21swapper/023:05:200
28834099310,30cyclictest0-21swapper/022:02:020
28834099310,30cyclictest0-21swapper/021:45:030
28834099310,30cyclictest0-21swapper/000:36:290
28834099310,30cyclictest0-21swapper/000:11:270
28836499300,29cyclictest357510-21diskmemload21:47:187
28836499300,1cyclictest590097-21munin-run00:34:597
288356993028,2cyclictest0-21swapper/523:04:345
288356993027,3cyclictest0-21swapper/522:17:315
288356993027,2cyclictest357510-21diskmemload21:55:245
288356993026,4cyclictest0-21swapper/522:00:205
28835699300,29cyclictest0-21swapper/521:00:115
28835699300,28cyclictest0-21swapper/523:35:505
28835699300,28cyclictest0-21swapper/522:54:095
28835699300,28cyclictest0-21swapper/521:25:575
28835699300,27cyclictest0-21swapper/522:21:485
28835699300,0cyclictest0-21swapper/523:41:565
28835699300,0cyclictest0-21swapper/523:05:075
28835699300,0cyclictest0-21swapper/522:59:305
28835699300,0cyclictest0-21swapper/521:45:135
28835699300,0cyclictest0-21swapper/519:11:385
28835699300,0cyclictest0-21swapper/500:16:555
288350993027,2cyclictest0-21swapper/323:58:073
28835099300,30cyclictest0-21swapper/322:02:013
28835099300,30cyclictest0-21swapper/300:30:413
28835099300,30cyclictest0-21swapper/300:00:103
28835099300,29cyclictest493442-21turbostat.cron23:10:013
28835099300,29cyclictest357510-21diskmemload21:22:453
28835099300,29cyclictest291155-21latency_hist19:15:013
28835099300,29cyclictest0-21swapper/323:40:153
28835099300,29cyclictest0-21swapper/323:11:163
28835099300,29cyclictest0-21swapper/300:12:323
28835099300,1cyclictest0-21swapper/323:22:243
28835099300,1cyclictest0-21swapper/321:45:023
288345993029,1cyclictest0-21swapper/223:40:492
28834599301,29cyclictest63850irq/124-eno122:25:252
28834599300,28cyclictest0-21swapper/222:36:402
288342993030,0cyclictest0-21swapper/122:30:271
288340993028,2cyclictest0-21swapper/023:22:370
288340993028,2cyclictest0-21swapper/000:17:070
288340993027,3cyclictest0-21swapper/021:26:010
288340993027,3cyclictest0-21swapper/000:25:290
28834099300,30cyclictest0-21swapper/023:52:130
28834099300,30cyclictest0-21swapper/023:46:130
28834099300,30cyclictest0-21swapper/023:36:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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