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2024-07-12 - 15:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Thu Jul 11, 2024 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6586
"cycles":100000000,6585
"load":"idle",6584
"condition":{6583
"clock":"3400"6581
"family":"x86",6580
"vendor":"Intel",6579
"processor":{6577
"dataset":"2024-01-08T15:37:47+0100"6575
"origin":"2024-01-08T12:43:21+0100",6574
"timestamps":{6573
"granularity":"microseconds"6571
2013:51:116569
18,13:51:096568
18,13:51:096567
19,13:51:106566
18,13:51:096565
18,13:51:096564
18,13:51:096563
18,13:51:096562
"maxima":[6561
013:50:516558
0,13:50:516557
0,13:50:516556
0,13:50:516555
0,13:50:516554
0,13:50:516553
0,13:50:516552
0,13:50:516551
0,13:50:516550
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0,13:50:516547
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0,13:50:516541
0,13:50:516540
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0,13:50:516536
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0,13:50:516529
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0,13:50:516527
0,13:50:516526
0,13:50:516525
0,13:50:516524
0,13:50:516523
0,13:50:516522
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0,13:50:516511
0,13:50:516510
0,13:50:516509
0,13:50:516508
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0,13:50:516504
0,13:50:516503
0,13:50:516502
0,13:50:516501
0,13:50:516500
0,13:50:516499
0,13:50:516498
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0,13:50:516495
0,13:50:516494
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0,13:50:516484
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0,13:50:516481
0,13:50:516480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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