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2021-07-29 - 03:53

Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Thu Jul 29, 2021 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
439428463,8sleep70-21swapper/716:34:457
442127362,8sleep60-21swapper/616:35:086
442626746,8sleep20-21swapper/216:35:122
443726443,8sleep40-21swapper/416:35:224
445825645,8sleep50-21swapper/516:35:395
446225544,8sleep00-21swapper/016:35:420
426625544,8sleep30-21swapper/316:32:573
420824939,7sleep10-21swapper/116:32:071
464899190,18cyclictest0-21swapper/220:02:592
468699160,15cyclictest0-21swapper/719:55:547
467899160,15cyclictest0-21swapper/621:02:356
467899160,15cyclictest0-21swapper/620:18:116
467899160,15cyclictest0-21swapper/619:48:436
467899160,15cyclictest0-21swapper/619:22:456
467899160,15cyclictest0-21swapper/619:07:016
467899160,15cyclictest0-21swapper/619:02:136
467899160,15cyclictest0-21swapper/618:52:086
4671991613,2cyclictest0-21swapper/520:05:275
467199160,15cyclictest0-21swapper/521:51:125
467199160,15cyclictest0-21swapper/520:36:415
467199160,15cyclictest0-21swapper/520:12:195
4641991613,2cyclictest0-21swapper/116:41:011
464199160,15cyclictest0-21swapper/121:16:131
464199160,15cyclictest0-21swapper/120:19:041
4686991512,2cyclictest0-21swapper/721:21:017
4686991512,2cyclictest0-21swapper/718:41:157
4678991512,2cyclictest0-21swapper/621:05:566
467899150,14cyclictest0-21swapper/620:36:166
467199150,14cyclictest0-21swapper/520:19:115
467199150,14cyclictest0-21swapper/519:48:355
467199150,14cyclictest0-21swapper/519:21:585
465599150,14cyclictest0-21swapper/321:15:363
4648991512,2cyclictest0-21swapper/219:23:312
464899150,14cyclictest0-21swapper/220:19:052
464899150,14cyclictest0-21swapper/218:41:582
4641991512,2cyclictest0-21swapper/121:22:451
4641991512,2cyclictest0-21swapper/120:13:051
4641991512,2cyclictest0-21swapper/116:36:051
464199150,14cyclictest0-21swapper/121:00:501
464199150,14cyclictest0-21swapper/119:57:251
464199150,14cyclictest0-21swapper/119:22:101
464199150,14cyclictest0-21swapper/118:52:001
464199150,14cyclictest0-21swapper/118:42:151
4686991411,2cyclictest0-21swapper/720:03:447
468699140,13cyclictest0-21swapper/719:50:167
4678991411,2cyclictest0-21swapper/620:47:086
4678991411,2cyclictest0-21swapper/620:32:026
4678991411,2cyclictest0-21swapper/620:13:146
4678991411,2cyclictest0-21swapper/620:03:396
467899140,13cyclictest0-21swapper/622:04:146
467899140,13cyclictest0-21swapper/621:16:136
467899140,13cyclictest0-21swapper/619:57:056
4671991411,2cyclictest0-21swapper/521:59:175
4671991411,2cyclictest0-21swapper/521:39:235
4671991411,2cyclictest0-21swapper/521:10:265
4671991411,2cyclictest0-21swapper/520:54:165
4671991411,2cyclictest0-21swapper/520:32:035
4671991411,2cyclictest0-21swapper/520:28:245
467199140,13cyclictest0-21swapper/522:04:395
467199140,13cyclictest0-21swapper/519:36:065
467199140,13cyclictest0-21swapper/518:51:395
4655991411,2cyclictest0-21swapper/320:34:333
4655991411,2cyclictest0-21swapper/317:01:003
465599140,13cyclictest0-21swapper/320:18:423
465599140,13cyclictest0-21swapper/319:21:543
4648991411,2cyclictest0-21swapper/221:58:592
4648991411,2cyclictest0-21swapper/220:30:572
464899140,13cyclictest0-21swapper/221:51:102
464899140,13cyclictest0-21swapper/220:36:332
464899140,13cyclictest0-21swapper/219:48:252
4641991411,2cyclictest0-21swapper/121:59:091
4641991411,2cyclictest0-21swapper/121:39:111
4641991411,2cyclictest0-21swapper/121:10:291
4641991411,2cyclictest0-21swapper/120:54:211
4641991411,2cyclictest0-21swapper/120:32:061
4641991411,2cyclictest0-21swapper/120:28:241
4641991411,2cyclictest0-21swapper/120:05:391
4641991411,2cyclictest0-21swapper/120:04:181
464199140,13cyclictest0-21swapper/122:00:481
464199140,13cyclictest0-21swapper/121:51:401
464199140,13cyclictest0-21swapper/120:46:011
464199140,13cyclictest0-21swapper/120:36:201
464199140,13cyclictest0-21swapper/119:48:351
464199140,13cyclictest0-21swapper/119:07:031
464199140,13cyclictest0-21swapper/119:02:151
4678991311,2cyclictest0-21swapper/621:22:566
4678991311,1cyclictest0-21swapper/620:28:146
467899130,12cyclictest0-21swapper/618:43:596
4671991311,2cyclictest0-21swapper/519:51:005
465599130,12cyclictest0-21swapper/320:06:003
464899130,12cyclictest0-21swapper/221:00:462
464899130,12cyclictest0-21swapper/220:12:242
464199130,12cyclictest0-21swapper/121:29:301
4671991211,1cyclictest0-21swapper/520:46:545
4648991211,1cyclictest0-21swapper/220:28:152
464899120,1cyclictest0-21swapper/220:40:502
465599110,10cyclictest0-21swapper/319:54:253
465599110,10cyclictest0-21swapper/318:24:433
464899114,6cyclictest2128-21basename18:35:572
464899111,1cyclictest182350irq/27-eth021:40:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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