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2022-12-05 - 04:56

x86 Intel Core i7-3770 @3400 MHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Mon Dec 05, 2022 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3114828352,8sleep60-21swapper/614:34:386
3118727756,8sleep70-21swapper/714:35:117
3122227655,8sleep50-21swapper/514:35:415
3112626241,8sleep40-21swapper/414:34:204
3122626039,8sleep00-21swapper/014:35:440
3140825232,7sleep20-21swapper/214:38:192
3137125231,8sleep30-21swapper/314:37:483
3129325232,8sleep10-21swapper/114:36:421
3157399170,16cyclictest0-21swapper/719:36:497
3157299170,16cyclictest0-21swapper/619:09:576
3157299170,16cyclictest0-21swapper/618:51:556
3157299170,16cyclictest0-21swapper/618:21:256
3157199170,16cyclictest0-21swapper/515:13:555
3157199170,16cyclictest0-21swapper/515:13:555
3157099170,16cyclictest0-21swapper/419:24:274
3157099170,16cyclictest0-21swapper/417:24:164
3157399160,15cyclictest0-21swapper/718:52:357
3157399160,15cyclictest0-21swapper/718:23:337
3157399160,15cyclictest0-21swapper/718:21:287
3157399160,15cyclictest0-21swapper/718:09:267
3157399160,15cyclictest0-21swapper/717:05:347
3157399160,15cyclictest0-21swapper/716:54:447
3157399160,15cyclictest0-21swapper/715:48:577
31572991613,2cyclictest0-21swapper/620:03:436
31572991613,2cyclictest0-21swapper/619:08:186
3157299160,15cyclictest0-21swapper/619:50:016
3157299160,15cyclictest0-21swapper/618:16:386
3157299160,15cyclictest0-21swapper/618:09:006
3157299160,15cyclictest0-21swapper/617:55:176
3157299160,15cyclictest0-21swapper/617:08:496
3157299160,15cyclictest0-21swapper/616:45:466
3157199160,15cyclictest0-21swapper/519:42:405
3157199160,15cyclictest0-21swapper/518:30:465
3157199160,15cyclictest0-21swapper/518:09:115
3157199160,15cyclictest0-21swapper/515:09:025
31570991613,2cyclictest0-21swapper/420:04:184
31570991613,2cyclictest0-21swapper/419:58:414
31570991613,2cyclictest0-21swapper/419:35:304
3157099160,15cyclictest0-21swapper/419:18:464
3157099160,15cyclictest0-21swapper/417:57:244
3157099160,15cyclictest0-21swapper/417:29:454
3157099160,15cyclictest0-21swapper/417:04:254
3157099160,15cyclictest0-21swapper/416:48:404
3157099160,15cyclictest0-21swapper/416:45:444
3156999160,15cyclictest0-21swapper/319:34:543
3156899160,15cyclictest0-21swapper/218:17:272
3157399150,14cyclictest0-21swapper/719:42:067
3157399150,14cyclictest0-21swapper/717:24:417
3157299150,14cyclictest0-21swapper/620:03:246
3157299150,14cyclictest0-21swapper/619:48:216
3157299150,14cyclictest0-21swapper/619:36:236
3157299150,14cyclictest0-21swapper/618:54:166
3157299150,14cyclictest0-21swapper/617:17:126
3157199150,14cyclictest0-21swapper/519:35:225
3157199150,14cyclictest0-21swapper/519:10:045
3157199150,14cyclictest0-21swapper/518:23:035
3157199150,14cyclictest0-21swapper/517:57:465
3157099150,14cyclictest0-21swapper/418:51:464
3157099150,14cyclictest0-21swapper/418:23:334
3157099150,14cyclictest0-21swapper/417:15:054
3157099150,14cyclictest0-21swapper/415:58:564
31569991512,2cyclictest0-21swapper/319:39:333
3156999150,14cyclictest0-21swapper/318:08:553
3156999150,14cyclictest0-21swapper/317:58:003
3156999150,14cyclictest0-21swapper/317:04:263
3156999150,14cyclictest0-21swapper/316:48:403
3156899150,14cyclictest0-21swapper/218:52:372
3156899150,14cyclictest0-21swapper/218:23:102
3156899150,14cyclictest0-21swapper/217:55:152
3156899150,14cyclictest0-21swapper/216:54:412
31559991512,2cyclictest0-21swapper/020:04:020
3155999150,14cyclictest0-21swapper/019:47:350
3155999150,14cyclictest0-21swapper/019:36:450
3155999150,14cyclictest0-21swapper/019:10:030
3155999150,14cyclictest0-21swapper/018:52:310
3155999150,14cyclictest0-21swapper/018:39:570
3155999150,14cyclictest0-21swapper/018:23:020
3155999150,14cyclictest0-21swapper/017:57:540
3155999150,14cyclictest0-21swapper/017:15:190
3157399140,13cyclictest0-21swapper/719:43:577
3157399140,13cyclictest0-21swapper/717:17:047
3157399140,13cyclictest0-21swapper/716:48:597
31572991411,2cyclictest0-21swapper/619:39:156
31572991411,2cyclictest0-21swapper/618:43:406
3157299140,13cyclictest0-21swapper/619:28:526
3157299140,13cyclictest0-21swapper/619:18:436
3157299140,13cyclictest0-21swapper/618:39:536
3157299140,13cyclictest0-21swapper/618:00:136
3157299140,13cyclictest0-21swapper/617:04:096
3157299140,13cyclictest0-21swapper/615:53:556
31571991411,2cyclictest0-21swapper/519:07:275
3157199140,13cyclictest0-21swapper/519:24:235
3157199140,13cyclictest0-21swapper/518:13:515
3157199140,13cyclictest0-21swapper/517:15:215
3157199140,13cyclictest0-21swapper/517:04:055
3157199140,13cyclictest0-21swapper/516:40:005
31570991411,2cyclictest0-21swapper/418:59:024
31570991411,2cyclictest0-21swapper/418:53:544
3157099140,13cyclictest0-21swapper/419:50:054
3157099140,13cyclictest0-21swapper/419:38:444
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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