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2021-10-16 - 13:27

Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Sat Oct 16, 2021 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2427728160,8sleep40-21swapper/415:25:414
2419027555,7sleep60-21swapper/615:24:316
2406226544,8sleep70-21swapper/715:22:407
2423526150,8sleep30-21swapper/315:25:083
2427825938,8sleep50-21swapper/515:25:425
2415025545,7sleep20-21swapper/215:23:552
2424225443,8sleep10-21swapper/115:25:141
2296525332,8sleep00-21swapper/015:21:040
2449599180,17cyclictest0-21swapper/418:29:244
24505991714,2cyclictest0-21swapper/520:09:475
2449599170,16cyclictest0-21swapper/420:51:304
2449599170,16cyclictest0-21swapper/420:49:044
2449599170,16cyclictest0-21swapper/418:20:214
2452199160,15cyclictest0-21swapper/720:51:327
2452199160,15cyclictest0-21swapper/720:47:137
2452199160,15cyclictest0-21swapper/718:20:117
2452199160,10cyclictest0-21swapper/718:28:267
24505991613,2cyclictest0-21swapper/518:20:065
2450599160,15cyclictest0-21swapper/520:52:295
2450599160,15cyclictest0-21swapper/520:16:355
2450599160,15cyclictest0-21swapper/519:46:365
2450599160,15cyclictest0-21swapper/518:28:475
24495991613,2cyclictest0-21swapper/418:42:464
2449599160,15cyclictest0-21swapper/420:16:334
2448799160,15cyclictest0-21swapper/319:44:423
2447399160,15cyclictest0-21swapper/119:53:411
2452199150,14cyclictest0-21swapper/719:44:407
24513991512,2cyclictest0-21swapper/620:10:496
24505991513,1cyclictest0-21swapper/519:57:115
2450599150,14cyclictest0-21swapper/520:46:355
2448799150,14cyclictest0-21swapper/320:47:123
2448799150,14cyclictest0-21swapper/318:28:583
2448799150,14cyclictest0-21swapper/318:20:343
24473991512,2cyclictest0-21swapper/120:09:491
24473991512,2cyclictest0-21swapper/118:10:021
24473991512,2cyclictest0-21swapper/117:40:201
2447399150,14cyclictest0-21swapper/120:52:211
2447399150,14cyclictest0-21swapper/120:46:361
2447399150,14cyclictest0-21swapper/119:46:561
2447399150,14cyclictest0-21swapper/119:36:571
2447399150,14cyclictest0-21swapper/118:58:491
2447399150,14cyclictest0-21swapper/118:19:541
24465991511,4cyclictest0-21swapper/020:27:050
24521991411,2cyclictest0-21swapper/720:26:587
24521991411,2cyclictest0-21swapper/720:10:157
24521991411,2cyclictest0-21swapper/719:00:557
24521991411,2cyclictest0-21swapper/718:41:507
24521991411,2cyclictest0-21swapper/718:12:427
24521991411,2cyclictest0-21swapper/718:09:567
24521991411,2cyclictest0-21swapper/718:01:317
24521991411,2cyclictest0-21swapper/717:31:427
2452199140,13cyclictest0-21swapper/720:43:057
24513991411,2cyclictest0-21swapper/620:10:126
24513991411,2cyclictest0-21swapper/618:12:346
24513991411,2cyclictest0-21swapper/618:01:386
24505991411,2cyclictest0-21swapper/520:36:165
24505991411,2cyclictest0-21swapper/518:55:155
24505991411,2cyclictest0-21swapper/518:42:305
24505991411,2cyclictest0-21swapper/518:32:225
24505991411,2cyclictest0-21swapper/518:01:465
24505991411,2cyclictest0-21swapper/517:55:465
2450599140,13cyclictest0-21swapper/519:54:295
2450599140,13cyclictest0-21swapper/519:28:235
2450599140,13cyclictest0-21swapper/519:24:025
2450599140,13cyclictest0-21swapper/518:58:575
2450599140,13cyclictest0-21swapper/518:46:205
2450599140,13cyclictest0-21swapper/518:20:565
24495991411,2cyclictest0-21swapper/420:10:034
24495991411,2cyclictest0-21swapper/418:55:064
24495991411,2cyclictest0-21swapper/418:32:214
24495991411,2cyclictest0-21swapper/418:09:564
24495991411,2cyclictest0-21swapper/418:01:394
24495991411,2cyclictest0-21swapper/417:40:224
24495991411,2cyclictest0-21swapper/417:30:564
2449599140,13cyclictest0-21swapper/419:54:164
2449599140,13cyclictest0-21swapper/419:45:534
2449599140,13cyclictest0-21swapper/418:46:554
24487991411,2cyclictest0-21swapper/319:57:133
24487991411,2cyclictest0-21swapper/319:35:553
24487991411,2cyclictest0-21swapper/318:43:443
24487991411,2cyclictest0-21swapper/318:09:553
24487991411,2cyclictest0-21swapper/318:05:363
24487991411,2cyclictest0-21swapper/317:50:413
24487991411,2cyclictest0-21swapper/317:40:293
2448799140,13cyclictest0-21swapper/320:06:513
2448799140,13cyclictest0-21swapper/319:05:553
24473991411,2cyclictest0-21swapper/119:57:121
24473991411,2cyclictest0-21swapper/118:31:431
24473991411,2cyclictest0-21swapper/118:12:061
24473991411,2cyclictest0-21swapper/118:01:471
24473991411,2cyclictest0-21swapper/117:51:341
24473991411,2cyclictest0-21swapper/117:30:381
2447399140,13cyclictest0-21swapper/120:16:401
2447399140,13cyclictest0-21swapper/118:41:561
2447399140,13cyclictest0-21swapper/118:28:371
24465991411,2cyclictest0-21swapper/020:20:530
24465991411,2cyclictest0-21swapper/019:57:100
24465991411,2cyclictest0-21swapper/019:00:550
24465991411,2cyclictest0-21swapper/018:55:050
24465991411,2cyclictest0-21swapper/018:41:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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