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2022-06-30 - 19:02

x86 Intel Core i7-3770 @3400 MHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack8slot5.osadl.org (updated Thu Jun 30, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2646227352,8sleep70-21swapper/704:58:087
2641127151,7sleep40-21swapper/404:57:254
2635926747,7sleep20-21swapper/204:56:432
2621426636,7sleep50-21swapper/504:54:385
2640426139,7sleep60-21swapper/604:57:196
2633925837,8sleep00-21swapper/004:56:250
2645425736,8sleep10-21swapper/104:58:021
2617425635,8sleep30-21swapper/304:54:043
2662399170,16cyclictest0-21swapper/408:56:494
2662399170,16cyclictest0-21swapper/407:23:314
2660899170,16cyclictest0-21swapper/007:22:560
26642991613,2cyclictest0-21swapper/607:51:096
2664299160,15cyclictest0-21swapper/610:12:406
2664299160,15cyclictest0-21swapper/607:20:466
26632991613,2cyclictest0-21swapper/509:12:565
2663299160,15cyclictest0-21swapper/510:18:325
2663299160,15cyclictest0-21swapper/510:15:355
2663299160,15cyclictest0-21swapper/510:12:575
2663299160,15cyclictest0-21swapper/507:22:485
2663299160,15cyclictest0-21swapper/507:12:325
2662399160,15cyclictest0-21swapper/410:19:354
2662399160,15cyclictest0-21swapper/409:33:264
2662399160,15cyclictest0-21swapper/407:19:514
2661699160,15cyclictest0-21swapper/310:15:363
26610991613,2cyclictest0-21swapper/207:37:182
2661099160,15cyclictest0-21swapper/210:15:082
26609991613,2cyclictest0-21swapper/109:21:121
26609991613,2cyclictest0-21swapper/108:38:101
26609991613,2cyclictest0-21swapper/108:38:101
26608991613,2cyclictest0-21swapper/009:20:420
26608991613,2cyclictest0-21swapper/007:32:190
2664899150,14cyclictest0-21swapper/710:19:347
26642991512,2cyclictest0-21swapper/607:31:276
26632991513,2cyclictest0-21swapper/507:51:005
26632991513,1cyclictest0-21swapper/509:20:015
26610991512,2cyclictest0-21swapper/209:20:322
26610991512,2cyclictest0-21swapper/208:02:492
26610991512,2cyclictest0-21swapper/207:28:112
26610991512,2cyclictest0-21swapper/206:33:242
2661099150,14cyclictest0-21swapper/208:57:382
2661099150,14cyclictest0-21swapper/207:22:352
26609991512,2cyclictest0-21swapper/107:48:461
2660999150,14cyclictest0-21swapper/110:18:411
2660999150,14cyclictest0-21swapper/110:14:411
2660999150,14cyclictest0-21swapper/110:12:051
2660999150,14cyclictest0-21swapper/107:19:501
2660999150,14cyclictest0-21swapper/107:12:361
26608991512,2cyclictest0-21swapper/009:12:330
2660899150,14cyclictest0-21swapper/008:57:510
26648991411,2cyclictest0-21swapper/708:02:377
26648991411,2cyclictest0-21swapper/707:52:377
26648991411,2cyclictest0-21swapper/707:32:517
26648991411,2cyclictest0-21swapper/705:58:147
2664899140,13cyclictest0-21swapper/710:15:337
2664899140,13cyclictest0-21swapper/707:22:287
2664899140,13cyclictest0-21swapper/707:13:247
26642991411,2cyclictest0-21swapper/609:18:596
26642991411,2cyclictest0-21swapper/608:02:486
26642991411,2cyclictest0-21swapper/607:46:206
26642991411,2cyclictest0-21swapper/607:37:166
26642991411,2cyclictest0-21swapper/607:06:456
2664299140,13cyclictest0-21swapper/610:19:126
2664299140,13cyclictest0-21swapper/610:14:316
2664299140,13cyclictest0-21swapper/609:28:226
2664299140,13cyclictest0-21swapper/608:56:516
2664299140,13cyclictest0-21swapper/608:47:236
2664299140,13cyclictest0-21swapper/607:12:536
26632991411,2cyclictest0-21swapper/508:36:045
26632991411,2cyclictest0-21swapper/508:02:445
26632991411,2cyclictest0-21swapper/507:43:345
26632991411,2cyclictest0-21swapper/507:29:525
2663299140,13cyclictest0-21swapper/508:56:485
2663299140,13cyclictest0-21swapper/508:46:515
26623991411,2cyclictest0-21swapper/409:18:184
26623991411,2cyclictest0-21swapper/408:03:104
26623991411,2cyclictest0-21swapper/407:51:284
26623991411,2cyclictest0-21swapper/407:44:434
26623991411,2cyclictest0-21swapper/407:37:304
26623991411,2cyclictest0-21swapper/407:29:494
26623991411,2cyclictest0-21swapper/406:58:134
26623991411,2cyclictest0-21swapper/406:43:334
2662399140,13cyclictest0-21swapper/410:14:564
2662399140,13cyclictest0-21swapper/410:08:204
2662399140,13cyclictest0-21swapper/409:28:234
26616991412,1cyclictest0-21swapper/307:52:353
26616991411,2cyclictest0-21swapper/309:19:093
26616991411,2cyclictest0-21swapper/308:02:373
26610991412,2cyclictest0-21swapper/209:12:272
26610991411,2cyclictest0-21swapper/209:31:432
26610991411,2cyclictest0-21swapper/207:51:172
26610991411,2cyclictest0-21swapper/207:44:482
26610991411,2cyclictest0-21swapper/207:30:232
26610991411,2cyclictest0-21swapper/205:48:322
2661099140,13cyclictest0-21swapper/210:20:222
2661099140,13cyclictest0-21swapper/210:12:222
2661099140,13cyclictest0-21swapper/208:46:592
26609991411,2cyclictest0-21swapper/109:13:061
26609991411,2cyclictest0-21swapper/108:03:101
26609991411,2cyclictest0-21swapper/107:58:541
26609991411,2cyclictest0-21swapper/107:30:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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