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2022-08-15 - 18:08

x86 Intel Core i7-3770 @3400 MHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack8slot5.osadl.org (updated Mon Aug 15, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188527453,8sleep70-21swapper/704:17:137
187127352,8sleep60-21swapper/604:17:046
184927150,8sleep50-21swapper/504:16:475
185825847,8sleep40-21swapper/404:16:544
335299570,26rtkit-daemon0-21swapper/204:12:322
183625737,7sleep10-21swapper/104:16:351
187425536,7sleep00-21swapper/004:17:060
172325231,8sleep30-21swapper/304:15:013
2068991714,2cyclictest0-21swapper/507:31:455
206899170,16cyclictest0-21swapper/506:21:445
207099160,15cyclictest0-21swapper/708:59:217
207099160,15cyclictest0-21swapper/706:22:417
2069991613,2cyclictest0-21swapper/608:11:096
2069991613,2cyclictest0-21swapper/607:15:276
206999160,15cyclictest0-21swapper/608:59:226
206999160,15cyclictest0-21swapper/608:43:596
206999160,15cyclictest0-21swapper/608:36:226
206999160,15cyclictest0-21swapper/608:23:246
206999160,15cyclictest0-21swapper/606:21:276
2068991613,2cyclictest0-21swapper/509:19:525
206899160,15cyclictest0-21swapper/508:58:565
205599160,15cyclictest0-21swapper/107:06:141
207099150,14cyclictest0-21swapper/707:13:177
206999150,14cyclictest0-21swapper/606:52:406
2068991513,2cyclictest0-21swapper/509:12:055
2068991513,2cyclictest0-21swapper/507:14:435
206899150,14cyclictest0-21swapper/507:06:175
206499150,14cyclictest0-21swapper/408:59:424
205899150,14cyclictest0-21swapper/308:36:573
205899150,14cyclictest0-21swapper/307:36:483
205899150,14cyclictest0-21swapper/306:27:443
205599150,14cyclictest0-21swapper/108:59:431
205599150,14cyclictest0-21swapper/108:37:011
205599150,14cyclictest0-21swapper/108:02:191
205599150,14cyclictest0-21swapper/106:42:261
205599150,14cyclictest0-21swapper/106:23:371
205599150,14cyclictest0-21swapper/105:57:411
207099147,7cyclictest0-21swapper/706:43:257
2070991413,1cyclictest0-21swapper/708:07:297
2070991411,2cyclictest0-21swapper/709:45:307
2070991411,2cyclictest0-21swapper/709:19:497
2070991411,2cyclictest0-21swapper/708:38:447
2070991411,2cyclictest0-21swapper/708:17:017
2070991411,2cyclictest0-21swapper/707:56:167
2070991411,2cyclictest0-21swapper/707:29:597
2070991411,2cyclictest0-21swapper/707:02:517
2070991411,2cyclictest0-21swapper/706:57:487
207099140,13cyclictest0-21swapper/708:36:267
207099140,13cyclictest0-21swapper/708:23:207
207099140,13cyclictest0-21swapper/707:36:467
2069991412,1cyclictest0-21swapper/608:04:506
2069991411,2cyclictest0-21swapper/609:45:586
2069991411,2cyclictest0-21swapper/608:14:306
2069991411,2cyclictest0-21swapper/607:02:276
206999140,13cyclictest0-21swapper/609:24:356
206999140,13cyclictest0-21swapper/609:05:146
206999140,13cyclictest0-21swapper/606:23:016
2068991411,2cyclictest0-21swapper/509:45:405
2068991411,2cyclictest0-21swapper/508:11:145
2068991411,2cyclictest0-21swapper/508:04:425
2068991411,2cyclictest0-21swapper/506:59:065
2068991411,2cyclictest0-21swapper/506:53:135
206899140,13cyclictest0-21swapper/506:23:305
2064991411,2cyclictest0-21swapper/407:30:074
2064991411,2cyclictest0-21swapper/407:16:534
206499140,13cyclictest0-21swapper/409:24:594
206499140,13cyclictest0-21swapper/408:36:384
206499140,13cyclictest0-21swapper/406:46:594
206499140,13cyclictest0-21swapper/406:23:364
2058991411,2cyclictest0-21swapper/309:45:103
2058991411,2cyclictest0-21swapper/308:12:443
2058991411,2cyclictest0-21swapper/307:31:073
2058991411,2cyclictest0-21swapper/307:17:393
205899140,13cyclictest0-21swapper/309:24:593
205899140,13cyclictest0-21swapper/308:59:023
205899140,13cyclictest0-21swapper/308:02:343
205899140,13cyclictest0-21swapper/307:13:113
205899140,13cyclictest0-21swapper/307:04:543
205899140,13cyclictest0-21swapper/306:21:353
2057991411,2cyclictest0-21swapper/209:45:082
2057991411,2cyclictest0-21swapper/208:16:532
2057991411,2cyclictest0-21swapper/207:31:452
2057991411,2cyclictest0-21swapper/207:07:492
2057991411,2cyclictest0-21swapper/206:59:002
205799140,13cyclictest0-21swapper/208:59:572
205799140,13cyclictest0-21swapper/207:13:172
205799140,13cyclictest0-21swapper/206:46:272
205799140,13cyclictest0-21swapper/206:27:502
205799140,13cyclictest0-21swapper/206:21:192
2055991411,2cyclictest0-21swapper/108:38:421
2055991411,2cyclictest0-21swapper/107:42:431
2055991411,2cyclictest0-21swapper/106:59:221
205599140,13cyclictest0-21swapper/109:24:561
205599140,13cyclictest0-21swapper/108:23:241
205599140,13cyclictest0-21swapper/107:13:521
2054991411,2cyclictest0-21swapper/009:45:330
2054991411,2cyclictest0-21swapper/008:07:460
2054991411,2cyclictest0-21swapper/007:16:530
205499140,13cyclictest0-21swapper/008:59:420
2070991311,2cyclictest0-21swapper/708:05:007
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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