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2024-05-29 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack8slot5.osadl.org (updated Wed May 29, 2024 00:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6586
"cycles":100000000,6585
"load":"idle",6584
"condition":{6583
"clock":"3400"6581
"family":"x86",6580
"vendor":"Intel",6579
"processor":{6577
"dataset":"2024-01-08T15:37:47+0100"6575
"origin":"2024-01-08T12:43:21+0100",6574
"timestamps":{6573
"granularity":"microseconds"6571
2013:51:116569
18,13:51:096568
18,13:51:096567
19,13:51:106566
18,13:51:096565
18,13:51:096564
18,13:51:096563
18,13:51:096562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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