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2023-10-01 - 21:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot5.osadl.org (updated Sun Oct 01, 2023 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
332499620,46rtkit-daemon0-21swapper/505:09:285
1569525130,18sleep30-21swapper/305:11:453
1567525130,18sleep10-21swapper/105:11:271
1583825029,8sleep40-21swapper/405:13:464
1553024827,8sleep60-21swapper/605:09:236
1552224726,8sleep70-21swapper/705:09:167
1565824130,8sleep20-21swapper/205:11:122
1553324029,8sleep00-21swapper/005:09:250
1600699157,5cyclictest0-21swapper/607:24:206
1600799140,13cyclictest0-21swapper/708:11:417
1600699140,13cyclictest0-21swapper/609:35:586
16005991411,2cyclictest0-21swapper/510:19:135
1600599140,13cyclictest0-21swapper/510:09:565
1600499140,13cyclictest0-21swapper/410:10:564
16002991411,2cyclictest0-21swapper/208:12:562
1600299140,13cyclictest0-21swapper/210:09:412
16001991411,2cyclictest0-21swapper/108:12:531
15998991411,2cyclictest0-21swapper/010:01:290
15998991411,2cyclictest0-21swapper/009:41:530
16006991311,1cyclictest0-21swapper/609:43:136
1600699130,12cyclictest0-21swapper/609:26:146
1600499130,12cyclictest0-21swapper/408:47:254
16002991311,2cyclictest0-21swapper/207:53:022
16002991311,2cyclictest0-21swapper/207:53:022
16001991311,1cyclictest0-21swapper/110:01:451
1599899130,12cyclictest0-21swapper/008:48:210
1600699129,2cyclictest0-21swapper/609:00:486
1600699120,11cyclictest0-21swapper/608:11:576
1600399120,11cyclictest0-21swapper/310:09:503
1599899120,11cyclictest0-21swapper/010:12:180
1600499118,2cyclictest0-21swapper/409:42:234
1600499118,2cyclictest0-21swapper/407:52:174
1600499118,2cyclictest0-21swapper/407:52:174
1600199118,2cyclictest0-21swapper/109:50:221
1600199118,2cyclictest0-21swapper/107:09:211
1599899118,2cyclictest0-21swapper/009:00:440
332499100,1rtkit-daemon3323-21rtkit-daemon09:45:461
332499100,1rtkit-daemon3323-21rtkit-daemon08:47:381
1600799107,2cyclictest0-21swapper/709:59:347
1600799100,9cyclictest0-21swapper/709:33:217
1600799100,9cyclictest0-21swapper/708:36:357
1600699108,2cyclictest0-21swapper/609:59:556
1600699100,9cyclictest0-21swapper/610:11:436
1600599107,2cyclictest0-21swapper/508:59:215
1600599100,9cyclictest0-21swapper/510:08:465
1600599100,9cyclictest0-21swapper/507:33:535
1600499107,2cyclictest0-21swapper/409:50:274
1600399100,9cyclictest0-21swapper/310:25:163
1600299108,2cyclictest0-21swapper/209:43:162
1600199107,2cyclictest0-21swapper/110:27:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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