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2021-01-21 - 06:41

Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot5.osadl.org (updated Thu Jan 21, 2021 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
590228766,8sleep40-21swapper/418:06:124
585528261,8sleep50-21swapper/518:05:335
586228161,7sleep30-21swapper/318:05:393
582827353,7sleep60-21swapper/618:05:106
572026949,7sleep20-21swapper/218:03:372
571626747,7sleep70-21swapper/718:03:347
594726029,8sleep10-21swapper/118:06:491
570725534,8sleep00-21swapper/018:03:270
6146991714,2cyclictest0-21swapper/521:53:515
6146991613,2cyclictest0-21swapper/522:35:315
6146991513,1cyclictest0-21swapper/521:01:225
6124991512,2cyclictest0-21swapper/221:52:452
6162991411,2cyclictest0-21swapper/721:24:127
6162991411,2cyclictest0-21swapper/720:07:517
6154991412,2cyclictest0-21swapper/621:23:016
6154991411,2cyclictest0-21swapper/622:35:386
6146991411,2cyclictest0-21swapper/522:20:295
6146991411,2cyclictest0-21swapper/521:22:195
6146991411,2cyclictest0-21swapper/521:21:445
6146991411,2cyclictest0-21swapper/521:03:365
614699140,13cyclictest0-21swapper/521:44:125
614699140,13cyclictest0-21swapper/520:26:335
6139991411,2cyclictest0-21swapper/421:03:194
6139991411,2cyclictest0-21swapper/421:00:414
6139991411,2cyclictest0-21swapper/419:57:234
6132991411,2cyclictest0-21swapper/322:35:423
6132991411,2cyclictest0-21swapper/321:23:563
6132991411,2cyclictest0-21swapper/319:22:213
613299140,13cyclictest0-21swapper/320:52:343
6124991411,2cyclictest0-21swapper/221:23:202
6124991411,2cyclictest0-21swapper/220:07:432
612499140,13cyclictest0-21swapper/220:23:432
6113991411,2cyclictest0-21swapper/122:57:241
6113991411,2cyclictest0-21swapper/122:19:581
6113991411,2cyclictest0-21swapper/121:54:131
6113991411,2cyclictest0-21swapper/121:42:131
6113991411,2cyclictest0-21swapper/121:22:351
6113991411,2cyclictest0-21swapper/121:01:221
6113991411,2cyclictest0-21swapper/120:09:481
611399140,13cyclictest0-21swapper/123:35:551
611399140,13cyclictest0-21swapper/123:18:121
6105991411,2cyclictest0-21swapper/022:19:550
610599140,13cyclictest0-21swapper/020:24:420
6162991311,2cyclictest0-21swapper/723:18:537
6154991311,1cyclictest0-21swapper/621:52:456
6132991311,2cyclictest0-21swapper/320:08:123
6113991311,2cyclictest0-21swapper/121:21:481
6105991311,1cyclictest0-21swapper/021:23:000
6105991311,1cyclictest0-21swapper/021:03:150
6105991311,1cyclictest0-21swapper/020:59:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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