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2022-06-29 - 15:46

x86 Intel Core i7-3770 @3400 MHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot5.osadl.org (updated Wed Jun 29, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
801428554,8sleep70-21swapper/704:57:267
794228150,8sleep40-21swapper/404:56:274
803126948,8sleep60-21swapper/604:57:416
802525938,8sleep00-21swapper/004:57:350
794325736,8sleep50-21swapper/504:56:285
800025342,8sleep20-21swapper/204:57:132
789225329,8sleep10-21swapper/104:55:431
783825231,8sleep30-21swapper/304:54:573
828099163,8cyclictest0-21swapper/707:05:257
8279991613,2cyclictest0-21swapper/608:43:136
827999160,15cyclictest0-21swapper/607:06:306
827899160,15cyclictest0-21swapper/510:25:385
827899160,15cyclictest0-21swapper/510:12:125
827899160,15cyclictest0-21swapper/509:13:165
827899160,15cyclictest0-21swapper/507:22:305
827499160,15cyclictest0-21swapper/410:24:414
828099158,3cyclictest0-21swapper/709:43:337
828099158,3cyclictest0-21swapper/709:22:087
828099158,3cyclictest0-21swapper/708:44:257
828099158,3cyclictest0-21swapper/708:06:037
828099158,3cyclictest0-21swapper/707:50:377
828099158,3cyclictest0-21swapper/707:50:377
828099158,3cyclictest0-21swapper/707:16:017
828099158,3cyclictest0-21swapper/707:04:057
828099153,7cyclictest0-21swapper/709:09:487
828099153,7cyclictest0-21swapper/708:52:177
828099153,7cyclictest0-21swapper/708:18:047
828099153,7cyclictest0-21swapper/708:10:157
828099153,7cyclictest0-21swapper/707:46:147
828099150,3cyclictest0-21swapper/705:22:397
827999150,14cyclictest0-21swapper/610:28:106
8278991512,2cyclictest0-21swapper/508:43:065
827899150,14cyclictest0-21swapper/506:59:475
827899150,14cyclictest0-21swapper/505:59:275
827499150,14cyclictest0-21swapper/405:24:284
826199150,14cyclictest0-21swapper/210:24:312
826199150,14cyclictest0-21swapper/207:00:162
8260991512,2cyclictest0-21swapper/108:43:151
826099150,14cyclictest0-21swapper/110:25:421
826099150,14cyclictest0-21swapper/106:59:291
828099148,3cyclictest0-21swapper/707:34:347
828099148,3cyclictest0-21swapper/706:49:267
828099148,2cyclictest0-21swapper/710:21:227
828099147,3cyclictest0-21swapper/710:15:427
828099147,3cyclictest0-21swapper/710:09:507
828099147,3cyclictest0-21swapper/710:03:247
828099147,3cyclictest0-21swapper/709:58:017
828099147,3cyclictest0-21swapper/709:45:177
828099147,3cyclictest0-21swapper/709:29:467
828099147,3cyclictest0-21swapper/709:26:167
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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