You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-07 - 18:35

x86 Intel Core i7-3770 @3400 MHz, Linux 3.18.69-rt75 (Profile)

Latency plot of system in rack #8, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot5.osadl.org (updated Wed Jun 07, 2023 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2988125827,8sleep40-21swapper/406:53:474
2988125827,8sleep40-21swapper/406:53:474
2986025129,8sleep30-21swapper/306:53:303
2986025129,8sleep30-21swapper/306:53:303
2986225029,8sleep50-21swapper/506:53:325
2986225029,8sleep50-21swapper/506:53:325
2984025029,8sleep10-21swapper/106:53:121
2984025029,8sleep10-21swapper/106:53:121
2982825029,8sleep70-21swapper/706:53:027
2982825029,8sleep70-21swapper/706:53:027
2815625029,8sleep00-21swapper/006:52:310
2815625029,8sleep00-21swapper/006:52:310
2792625029,8sleep60-21swapper/606:51:576
2792625029,8sleep60-21swapper/606:51:576
3007424130,8sleep20-21swapper/206:56:332
3007424130,8sleep20-21swapper/206:56:332
3024899160,9cyclictest0-21swapper/710:54:527
3024899158,7cyclictest0-21swapper/709:18:297
3024899158,3cyclictest0-21swapper/711:36:467
3024899158,3cyclictest0-21swapper/711:36:467
3024899158,3cyclictest0-21swapper/711:34:307
3024899158,3cyclictest0-21swapper/711:05:137
3024899158,3cyclictest0-21swapper/710:37:147
3024899158,3cyclictest0-21swapper/710:20:157
3024899158,3cyclictest0-21swapper/709:45:387
3024899153,9cyclictest0-21swapper/711:11:197
3024899150,8cyclictest0-21swapper/707:45:357
3024899148,3cyclictest0-21swapper/711:14:557
3024899147,7cyclictest0-21swapper/707:28:377
3024899147,3cyclictest0-21swapper/712:17:597
3024899147,3cyclictest0-21swapper/712:12:357
3024899147,3cyclictest0-21swapper/712:06:557
3024899147,3cyclictest0-21swapper/712:02:217
3024899147,3cyclictest0-21swapper/712:02:217
3024899147,3cyclictest0-21swapper/711:52:067
3024899147,3cyclictest0-21swapper/711:51:227
3024899147,3cyclictest0-21swapper/711:22:157
3024899147,3cyclictest0-21swapper/710:33:137
3024899147,3cyclictest0-21swapper/710:27:157
3024899147,3cyclictest0-21swapper/710:23:217
3024899147,3cyclictest0-21swapper/710:09:207
3024899147,3cyclictest0-21swapper/709:52:507
3024899147,3cyclictest0-21swapper/709:34:037
3024899147,3cyclictest0-21swapper/709:28:457
3024899147,3cyclictest0-21swapper/709:23:377
3024899147,3cyclictest0-21swapper/708:31:597
3024899147,3cyclictest0-21swapper/708:14:587
3024899147,3cyclictest0-21swapper/708:10:507
3024899147,3cyclictest0-21swapper/708:06:287
3024899147,3cyclictest0-21swapper/707:58:527
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional