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2024-10-04 - 00:51

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Thu Oct 03, 2024 12:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32016993534,1cyclictest28322-21fwupd12:24:422
32016993534,1cyclictest28322-21fwupd12:24:412
32016991919,0cyclictest61550irq/125-lan10:25:462
32016991918,1cyclictest61550irq/125-lan11:35:122
32016991918,1cyclictest61550irq/125-lan10:05:152
32016991918,1cyclictest61550irq/125-lan08:20:112
32016991918,1cyclictest61550irq/125-lan07:35:002
32016991818,0cyclictest61550irq/125-lan12:03:032
32016991818,0cyclictest61550irq/125-lan11:50:102
32016991818,0cyclictest61550irq/125-lan10:37:242
32016991818,0cyclictest61550irq/125-lan09:55:332
32016991818,0cyclictest61550irq/125-lan09:00:142
32016991818,0cyclictest61550irq/125-lan08:46:382
32016991817,1cyclictest61550irq/125-lan12:18:212
32016991817,1cyclictest61550irq/125-lan12:07:312
32016991817,1cyclictest61550irq/125-lan11:27:462
32016991817,1cyclictest61550irq/125-lan10:50:152
32016991817,1cyclictest61550irq/125-lan10:40:272
32016991817,1cyclictest61550irq/125-lan10:32:042
32016991817,1cyclictest61550irq/125-lan09:25:192
32016991817,1cyclictest61550irq/125-lan09:20:132
32016991817,1cyclictest61550irq/125-lan08:32:302
32016991816,1cyclictest61550irq/125-lan12:32:452
32016991816,1cyclictest61550irq/125-lan11:33:002
32016991816,1cyclictest61550irq/125-lan10:16:302
32016991717,0cyclictest61550irq/125-lan09:40:362
32016991717,0cyclictest61550irq/125-lan08:06:472
32016991716,1cyclictest61550irq/125-lan12:35:402
32016991716,1cyclictest61550irq/125-lan12:25:172
32016991716,1cyclictest61550irq/125-lan11:45:152
32016991716,1cyclictest61550irq/125-lan11:42:212
32016991716,1cyclictest61550irq/125-lan11:15:182
32016991716,1cyclictest61550irq/125-lan11:10:152
32016991716,1cyclictest61550irq/125-lan11:00:152
32016991716,1cyclictest61550irq/125-lan10:55:122
32016991716,1cyclictest61550irq/125-lan09:35:212
32016991716,1cyclictest61550irq/125-lan09:30:032
32016991716,1cyclictest61550irq/125-lan09:12:302
32016991716,1cyclictest61550irq/125-lan08:52:352
32016991616,0cyclictest61550irq/125-lan11:56:592
32016991616,0cyclictest61550irq/125-lan10:23:352
32016991616,0cyclictest61550irq/125-lan10:10:252
32016991616,0cyclictest61550irq/125-lan10:00:212
32016991616,0cyclictest61550irq/125-lan07:59:452
32016991615,1cyclictest61550irq/125-lan12:10:092
32016991615,1cyclictest61550irq/125-lan11:20:122
32016991615,1cyclictest61550irq/125-lan11:06:452
32016991615,1cyclictest61550irq/125-lan10:47:512
32016991615,1cyclictest61550irq/125-lan09:51:262
32016991615,1cyclictest61550irq/125-lan09:46:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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