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2025-07-03 - 19:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Thu Jul 03, 2025 12:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14563991918,1cyclictest60250irq/125-lan09:35:152
14563991818,0cyclictest60250irq/125-lan12:35:182
14563991817,1cyclictest60250irq/125-lan11:05:172
14563991817,1cyclictest60250irq/125-lan10:25:232
14563991817,1cyclictest60250irq/125-lan09:15:132
14563991817,1cyclictest60250irq/125-lan07:35:142
14563991817,1cyclictest60250irq/125-lan07:10:192
14563991717,0cyclictest60250irq/125-lan11:16:342
14563991717,0cyclictest60250irq/125-lan10:42:362
14563991716,1cyclictest60250irq/125-lan11:20:192
14563991716,1cyclictest60250irq/125-lan10:05:162
14563991716,1cyclictest60250irq/125-lan09:57:122
14563991716,1cyclictest60250irq/125-lan09:50:172
14563991716,1cyclictest60250irq/125-lan09:25:232
14563991716,1cyclictest60250irq/125-lan08:40:222
14563991716,1cyclictest60250irq/125-lan07:15:212
14563991616,0cyclictest60250irq/125-lan12:15:152
14563991616,0cyclictest60250irq/125-lan11:44:172
14563991616,0cyclictest60250irq/125-lan11:31:172
14563991616,0cyclictest60250irq/125-lan10:23:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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