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2022-05-28 - 14:55

x86 Intel Celeron G1620 @2700 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #8, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Sat May 28, 2022 12:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91699210,20cyclictest632-21irqbalance09:47:320
91699205,9cyclictest1418-21lxpanel07:50:130
91699201,12cyclictest12803-21ssh09:40:080
91699193,8cyclictest11893-21x2gopath10:17:290
91699190,10cyclictest7132-21x2gopath10:50:170
91699190,10cyclictest4360-21x2golistsession09:30:100
91699190,10cyclictest24977-21x2golistsession11:11:350
91699184,7cyclictest7198-21x2gopath10:11:550
91699182,8cyclictest2434-21x2gopath11:23:230
91699182,10cyclictest707-21Xorg08:14:120
91699181,9cyclictest32712-21x2golistsession12:38:100
91699181,9cyclictest29484-21x2golistsession11:55:370
91699181,9cyclictest28879-21x2golistsession09:59:120
91699181,9cyclictest2826-21x2golistsession07:11:310
91699181,9cyclictest25049-21x2golistsession12:29:040
91699181,9cyclictest18053-21x2golistsession07:36:220
91699181,9cyclictest14341-21x2golistsession10:20:180
91699181,10cyclictest7780-21x2golistsession12:08:270
91699181,10cyclictest28083-21x2golistsession10:36:480
91699180,9cyclictest9270-21x2golistsession09:36:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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