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2024-07-13 - 08:52

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7s.osadl.org (updated Sat Jul 13, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28263991918,1cyclictest55650irq/125-lan23:49:271
28263991918,1cyclictest55650irq/125-lan23:34:011
28263991918,1cyclictest55650irq/125-lan23:29:331
28263991918,1cyclictest55650irq/125-lan23:14:341
28263991918,1cyclictest55650irq/125-lan23:05:481
28263991918,1cyclictest55650irq/125-lan23:03:191
28263991918,1cyclictest55650irq/125-lan22:59:401
28263991918,1cyclictest55650irq/125-lan22:52:541
28263991918,1cyclictest55650irq/125-lan22:34:181
28263991918,1cyclictest55650irq/125-lan22:21:471
28263991918,1cyclictest55650irq/125-lan22:05:181
28263991918,1cyclictest55650irq/125-lan21:52:121
28263991918,1cyclictest55650irq/125-lan21:40:171
28263991918,1cyclictest55650irq/125-lan21:31:081
28263991918,1cyclictest55650irq/125-lan21:21:301
28263991918,1cyclictest55650irq/125-lan20:12:101
28263991918,1cyclictest55650irq/125-lan19:46:001
28263991918,1cyclictest55650irq/125-lan19:38:101
28263991918,1cyclictest55650irq/125-lan00:21:101
28263991917,1cyclictest55650irq/125-lan22:11:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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