You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-12-10 - 18:02

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7s.osadl.org (updated Sun Dec 10, 2023 12:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1715799370,37cyclictest1061-21meminfo09:20:250
1715799350,35cyclictest30194-21meminfo10:40:240
1715799350,34cyclictest17825-21meminfo11:35:260
1715799310,31cyclictest21458-21meminfo11:45:230
1715799310,29cyclictest6552-21meminfo09:35:240
1715799300,30cyclictest1424-21meminfo10:50:230
1715799290,29cyclictest3270-21meminfo10:55:250
1715799290,29cyclictest15289-21meminfo08:30:250
1715799280,28cyclictest2919-21meminfo09:25:260
1715799270,27cyclictest7262-21meminfo12:35:250
1715799270,27cyclictest6897-21meminfo11:05:210
1715799270,27cyclictest4382-21meminfo08:00:280
1715799270,27cyclictest11657-21meminfo08:20:260
1715799270,26cyclictest19117-21meminfo07:15:010
1715799270,26cyclictest1799-21meminfo12:20:250
1715799260,26cyclictest14179-21meminfo11:25:240
1715799260,25cyclictest3626-21meminfo12:25:220
1715799250,25cyclictest29839-21meminfo09:10:250
1715799250,25cyclictest19280-21meminfo10:10:210
1715799250,25cyclictest13476-21meminfo08:25:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional