You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-10-04 - 13:13

x86 Intel Celeron G1620 @2700 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #8, slot #7
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Tue Oct 04, 2022 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1019899211,19cyclictest3055-21python23:55:231
10198991816,1cyclictest0-21swapper/100:19:131
10198991715,1cyclictest18609-21x2gosqlitewrapp23:17:141
10197991717,0cyclictest0-21swapper/023:33:320
10197991715,1cyclictest6485-21x2golistsession21:52:210
1019799170,16cyclictest19436-21x2golistsession22:02:220
10198991614,1cyclictest1508-21x2golistsession21:48:521
1019899160,1cyclictest12501-21x2gosqlitewrapp19:13:111
1019899160,15cyclictest0-21swapper/122:43:121
1019899160,0cyclictest0-21swapper/121:10:051
1019799160,1cyclictest3416-21x2golistsession23:05:210
1019799160,1cyclictest24849-21x2gosqlitewrapp20:29:210
1019799160,16cyclictest0-21swapper/023:50:220
1019799160,15cyclictest0-21swapper/023:48:430
10198991513,1cyclictest0-21swapper/119:34:561
1019899150,15cyclictest0-21swapper/119:50:051
1019899150,15cyclictest0-21swapper/119:39:261
1019899150,0cyclictest0-21swapper/123:36:361
10197991515,0cyclictest0-21swapper/022:52:240
10197991515,0cyclictest0-21swapper/022:49:540
10197991515,0cyclictest0-21swapper/000:36:020
1019799150,15cyclictest0-21swapper/000:25:330
1019799150,15cyclictest0-21swapper/000:06:430
10198991414,0cyclictest0-21swapper/119:20:421
10197991414,0cyclictest0-21swapper/022:25:320
10197991414,0cyclictest0-21swapper/021:39:420
10197991414,0cyclictest0-21swapper/020:12:430
1019799140,14cyclictest0-21swapper/019:52:130
10198991313,0cyclictest0-21swapper/123:49:421
10198991313,0cyclictest0-21swapper/123:33:021
10198991313,0cyclictest0-21swapper/123:26:341
10198991311,1cyclictest0-21swapper/121:44:561
10197991313,0cyclictest0-21swapper/021:55:230
10197991313,0cyclictest0-21swapper/000:00:220
1019799130,13cyclictest0-21swapper/022:05:220
1019799130,12cyclictest0-21swapper/021:18:010
10198991212,0cyclictest0-21swapper/122:18:131
10198991212,0cyclictest0-21swapper/121:32:511
10198991212,0cyclictest0-21swapper/121:24:441
1019899120,12cyclictest0-21swapper/123:44:421
1019899120,12cyclictest0-21swapper/123:11:421
1019899120,12cyclictest0-21swapper/122:48:421
1019899120,12cyclictest0-21swapper/122:14:121
1019899120,0cyclictest0-21swapper/123:22:511
1019899120,0cyclictest0-21swapper/122:57:221
1019899120,0cyclictest0-21swapper/122:03:521
1019899120,0cyclictest0-21swapper/121:55:121
1019899120,0cyclictest0-21swapper/121:36:521
10197991212,0cyclictest0-21swapper/022:11:010
10197991212,0cyclictest0-21swapper/021:34:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional