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2026-05-16 - 11:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Sat May 16, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
732899310,31cyclictest325-21hwrng21:26:213
7313991817,1cyclictest59550irq/125-lan22:20:160
7313991817,1cyclictest59550irq/125-lan19:20:120
7313991817,1cyclictest59550irq/125-lan00:20:140
7313991817,1cyclictest59550irq/125-lan00:00:220
7313991717,0cyclictest59550irq/125-lan22:55:130
7313991717,0cyclictest59550irq/125-lan20:58:430
7313991717,0cyclictest59550irq/125-lan00:35:130
7313991716,1cyclictest59550irq/125-lan23:35:100
7313991716,1cyclictest59550irq/125-lan20:35:000
7313991716,1cyclictest59550irq/125-lan20:10:100
7313991716,1cyclictest59550irq/125-lan19:30:120
7313991716,1cyclictest59550irq/125-lan19:28:070
7313991716,1cyclictest59550irq/125-lan19:15:120
7313991716,1cyclictest59550irq/125-lan19:10:170
7313991716,1cyclictest59550irq/125-lan00:30:120
7313991616,0cyclictest59550irq/125-lan23:45:160
7313991615,1cyclictest59550irq/125-lan22:30:140
7313991615,1cyclictest59550irq/125-lan22:15:140
7313991615,1cyclictest59550irq/125-lan21:45:130
7313991615,1cyclictest59550irq/125-lan21:25:110
7313991615,1cyclictest59550irq/125-lan21:05:000
7313991615,1cyclictest59550irq/125-lan19:50:160
7326991515,0cyclictest325-21hwrng21:50:562
7321991515,0cyclictest325-21hwrng23:25:081
7321991515,0cyclictest325-21hwrng00:07:071
7313991515,0cyclictest59550irq/125-lan22:46:010
7313991515,0cyclictest59550irq/125-lan22:39:440
7313991515,0cyclictest59550irq/125-lan20:50:190
7313991515,0cyclictest59550irq/125-lan20:28:210
7313991515,0cyclictest59550irq/125-lan20:15:430
7313991515,0cyclictest59550irq/125-lan19:45:200
7313991514,1cyclictest59550irq/125-lan23:25:200
7313991514,1cyclictest59550irq/125-lan23:00:160
7313991514,1cyclictest59550irq/125-lan22:00:120
7313991514,1cyclictest59550irq/125-lan21:30:180
7313991514,1cyclictest59550irq/125-lan20:20:200
7313991514,1cyclictest59550irq/125-lan20:00:170
7313991514,1cyclictest59550irq/125-lan19:35:090
7326991414,0cyclictest325-21hwrng22:00:092
7326991414,0cyclictest325-21hwrng20:43:212
7321991414,0cyclictest325-21hwrng23:17:581
7321991414,0cyclictest325-21hwrng23:14:541
7321991414,0cyclictest325-21hwrng00:21:281
7313991414,0cyclictest59550irq/125-lan23:40:170
7313991414,0cyclictest59550irq/125-lan22:40:120
7313991414,0cyclictest59550irq/125-lan22:10:410
7313991414,0cyclictest59550irq/125-lan20:45:120
7313991414,0cyclictest325-21hwrng23:57:550
7313991414,0cyclictest325-21hwrng22:51:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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