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2025-07-03 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Thu Jul 03, 2025 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5579991818,0cyclictest60250irq/125-lan21:21:302
5579991817,1cyclictest60250irq/125-lan23:15:192
5579991817,1cyclictest60250irq/125-lan22:15:122
5579991817,1cyclictest60250irq/125-lan00:35:162
5579991717,0cyclictest60250irq/125-lan23:00:272
5579991717,0cyclictest60250irq/125-lan22:50:222
5579991716,1cyclictest60250irq/125-lan23:45:182
5579991716,1cyclictest60250irq/125-lan20:20:132
5579991716,1cyclictest60250irq/125-lan00:30:142
5579991616,0cyclictest60250irq/125-lan22:38:492
5579991616,0cyclictest60250irq/125-lan20:45:202
5579991616,0cyclictest60250irq/125-lan19:41:492
5579991616,0cyclictest60250irq/125-lan00:05:012
5579991615,1cyclictest60250irq/125-lan23:55:192
5579991615,1cyclictest60250irq/125-lan22:30:142
5579991615,1cyclictest60250irq/125-lan22:05:192
5579991615,1cyclictest60250irq/125-lan21:40:132
5579991615,1cyclictest60250irq/125-lan21:29:072
5579991615,1cyclictest60250irq/125-lan20:30:182
5579991615,1cyclictest60250irq/125-lan00:12:512
5579991515,0cyclictest60250irq/125-lan22:25:172
5579991515,0cyclictest60250irq/125-lan22:00:272
5579991515,0cyclictest60250irq/125-lan20:25:122
5579991515,0cyclictest60250irq/125-lan00:25:172
5579991515,0cyclictest329-21hwrng22:48:212
5579991515,0cyclictest329-21hwrng19:45:032
5579991515,0cyclictest329-21hwrng19:11:172
5579991515,0cyclictest329-21hwrng19:11:162
5579991515,0cyclictest329-21hwrng00:07:122
5579991514,1cyclictest60250irq/125-lan23:35:152
5579991514,1cyclictest60250irq/125-lan20:50:152
5579991514,1cyclictest60250irq/125-lan19:55:092
5579991514,1cyclictest60250irq/125-lan19:25:172
5579991414,0cyclictest60250irq/125-lan22:43:502
5579991414,0cyclictest60250irq/125-lan22:10:142
5579991414,0cyclictest60250irq/125-lan21:45:212
5579991414,0cyclictest60250irq/125-lan20:58:512
5579991414,0cyclictest60250irq/125-lan20:00:132
5579991414,0cyclictest60250irq/125-lan00:20:152
5579991414,0cyclictest329-21hwrng23:31:222
5579991414,0cyclictest329-21hwrng19:50:112
5579991413,1cyclictest60250irq/125-lan23:50:142
5579991413,1cyclictest60250irq/125-lan23:40:182
5579991413,1cyclictest60250irq/125-lan23:05:202
5579991413,1cyclictest60250irq/125-lan22:20:192
5579991413,1cyclictest60250irq/125-lan21:50:182
5579991413,1cyclictest60250irq/125-lan21:05:152
5579991413,1cyclictest60250irq/125-lan20:15:182
5579991413,1cyclictest60250irq/125-lan19:15:112
5579991313,0cyclictest60250irq/125-lan21:01:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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