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2025-12-16 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7.osadl.org (updated Tue Dec 16, 2025 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27116991918,1cyclictest59550irq/125-lan07:35:011
27116991817,1cyclictest59550irq/125-lan12:30:121
27116991817,1cyclictest59550irq/125-lan11:38:581
27116991817,1cyclictest59550irq/125-lan09:55:221
27116991717,0cyclictest59550irq/125-lan07:33:201
27116991716,1cyclictest59550irq/125-lan12:05:131
27116991716,1cyclictest59550irq/125-lan11:00:131
27116991716,1cyclictest59550irq/125-lan10:40:121
27116991716,1cyclictest59550irq/125-lan09:45:141
27116991716,1cyclictest59550irq/125-lan09:33:301
27116991716,1cyclictest59550irq/125-lan08:40:141
27116991716,1cyclictest59550irq/125-lan08:35:131
27116991716,1cyclictest59550irq/125-lan08:10:131
27116991615,1cyclictest59550irq/125-lan10:35:161
27116991615,1cyclictest59550irq/125-lan10:15:221
27116991615,1cyclictest59550irq/125-lan09:15:181
27116991615,1cyclictest59550irq/125-lan09:05:221
27116991615,1cyclictest59550irq/125-lan07:55:121
27116991515,0cyclictest59550irq/125-lan08:53:591
27116991515,0cyclictest59550irq/125-lan07:50:061
27116991514,1cyclictest59550irq/125-lan12:35:101
27116991514,1cyclictest59550irq/125-lan12:10:131
27116991514,1cyclictest59550irq/125-lan12:00:151
27116991514,1cyclictest59550irq/125-lan11:20:181
27116991514,1cyclictest59550irq/125-lan11:15:011
27116991514,1cyclictest59550irq/125-lan09:35:201
27116991514,1cyclictest59550irq/125-lan09:00:171
27116991514,1cyclictest59550irq/125-lan08:08:351
27120991414,0cyclictest325-21hwrng08:28:392
27116991414,0cyclictest59550irq/125-lan11:05:121
27116991414,0cyclictest59550irq/125-lan10:49:081
27116991414,0cyclictest59550irq/125-lan08:00:191
27116991414,0cyclictest59550irq/125-lan07:45:141
27116991413,1cyclictest59550irq/125-lan12:20:111
27116991413,1cyclictest59550irq/125-lan12:15:131
27116991413,1cyclictest59550irq/125-lan11:30:181
27116991413,1cyclictest59550irq/125-lan10:00:131
27116991413,1cyclictest59550irq/125-lan09:50:141
27116991413,1cyclictest59550irq/125-lan09:25:591
27116991413,1cyclictest59550irq/125-lan08:25:221
27125991313,0cyclictest325-21hwrng10:09:003
27116991313,0cyclictest59550irq/125-lan10:05:221
27116991312,1cyclictest59550irq/125-lan11:55:201
27116991312,1cyclictest59550irq/125-lan11:25:151
27116991312,1cyclictest59550irq/125-lan10:55:161
27116991312,1cyclictest59550irq/125-lan10:20:131
27116991312,1cyclictest59550irq/125-lan09:40:131
27116991312,1cyclictest59550irq/125-lan09:10:231
27116991312,1cyclictest59550irq/125-lan08:20:151
27116991312,1cyclictest59550irq/125-lan07:25:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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