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2024-10-09 - 05:18

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7s.osadl.org (updated Wed Oct 09, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24191992019,1cyclictest55650irq/125-lan00:30:110
24191991918,1cyclictest55650irq/125-lan23:50:170
24191991918,1cyclictest55650irq/125-lan23:36:510
24191991918,1cyclictest55650irq/125-lan22:43:330
24191991918,1cyclictest55650irq/125-lan22:38:380
24191991918,1cyclictest55650irq/125-lan22:31:220
24191991918,1cyclictest55650irq/125-lan22:30:010
24191991918,1cyclictest55650irq/125-lan22:23:500
24191991918,1cyclictest55650irq/125-lan22:06:460
24191991918,1cyclictest55650irq/125-lan21:45:140
24191991918,1cyclictest55650irq/125-lan21:43:050
24191991918,1cyclictest55650irq/125-lan21:25:190
24191991918,1cyclictest55650irq/125-lan21:20:160
24191991918,1cyclictest55650irq/125-lan20:55:370
24191991918,1cyclictest55650irq/125-lan20:30:150
24191991918,1cyclictest55650irq/125-lan20:00:470
24191991918,1cyclictest55650irq/125-lan19:30:530
24191991918,1cyclictest55650irq/125-lan00:18:350
24191991818,0cyclictest55650irq/125-lan23:00:120
24191991818,0cyclictest55650irq/125-lan22:56:150
24191991818,0cyclictest55650irq/125-lan21:18:580
24191991818,0cyclictest55650irq/125-lan21:13:190
24191991818,0cyclictest55650irq/125-lan20:44:010
24191991818,0cyclictest55650irq/125-lan20:35:050
24191991818,0cyclictest55650irq/125-lan19:48:150
24191991818,0cyclictest55650irq/125-lan00:20:260
24191991817,1cyclictest55650irq/125-lan23:55:090
24191991817,1cyclictest55650irq/125-lan23:45:330
24191991817,1cyclictest55650irq/125-lan23:41:120
24191991817,1cyclictest55650irq/125-lan23:33:080
24191991817,1cyclictest55650irq/125-lan23:20:390
24191991817,1cyclictest55650irq/125-lan23:17:270
24191991817,1cyclictest55650irq/125-lan22:45:130
24191991817,1cyclictest55650irq/125-lan22:10:180
24191991817,1cyclictest55650irq/125-lan22:00:100
24191991817,1cyclictest55650irq/125-lan21:56:300
24191991817,1cyclictest55650irq/125-lan21:50:170
24191991817,1cyclictest55650irq/125-lan21:35:150
24191991817,1cyclictest55650irq/125-lan21:32:330
24191991817,1cyclictest55650irq/125-lan20:50:150
24191991817,1cyclictest55650irq/125-lan19:50:130
24191991817,1cyclictest55650irq/125-lan19:37:380
24191991817,1cyclictest55650irq/125-lan00:38:170
24191991717,0cyclictest55650irq/125-lan23:11:110
24191991717,0cyclictest55650irq/125-lan20:45:400
24191991717,0cyclictest55650irq/125-lan00:28:110
24191991716,1cyclictest55650irq/125-lan23:26:290
24191991716,1cyclictest55650irq/125-lan23:05:000
24191991716,1cyclictest55650irq/125-lan22:50:440
24191991716,1cyclictest55650irq/125-lan22:15:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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