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2023-09-23 - 23:29

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack8slot7s.osadl.org (updated Sat Sep 23, 2023 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3123899360,36cyclictest7930-21meminfo09:00:260
3123899360,36cyclictest15553-21meminfo10:50:250
3123899340,34cyclictest586-21meminfo08:40:230
3123899310,31cyclictest14844-21meminfo07:50:240
3123899300,30cyclictest7347-21meminfo07:30:260
3123899300,29cyclictest640-21meminfo07:15:010
3123899290,29cyclictest29746-21meminfo10:00:240
3123899290,29cyclictest25755-21meminfo08:20:230
3123899290,28cyclictest4995-21meminfo11:50:220
3123899290,28cyclictest3704-21meminfo07:20:280
3123899280,28cyclictest18483-21meminfo08:00:280
3123899270,27cyclictest6466-21meminfo10:25:270
3123899270,27cyclictest4291-21meminfo08:50:250
3123899270,27cyclictest19188-21meminfo11:00:230
3123899270,27cyclictest15201-21meminfo09:20:250
3123899270,27cyclictest11017-21meminfo07:40:220
3123899270,26cyclictest17028-21meminfo09:25:280
3123899260,26cyclictest26462-21meminfo11:20:250
3123899260,26cyclictest10449-21meminfo12:05:240
3123899260,25cyclictest17729-21meminfo12:25:260
3123899250,25cyclictest24649-21meminfo11:15:280
3123899250,25cyclictest15910-21meminfo12:20:250
3123899250,25cyclictest11915-21meminfo10:40:220
3123899250,25cyclictest10099-21meminfo10:35:260
3123899250,24cyclictest9743-21meminfo09:05:240
3123899240,24cyclictest21012-21meminfo11:05:270
3123899240,24cyclictest20291-21meminfo08:05:210
3123899230,23cyclictest27577-21meminfo08:25:270
3123899230,23cyclictest22476-21meminfo09:40:250
3123899230,23cyclictest21363-21meminfo12:35:250
3123899230,23cyclictest12271-21meminfo12:10:230
3123899220,22cyclictest8638-21meminfo12:00:280
3123899220,22cyclictest23937-21meminfo08:15:270
3123899220,22cyclictest22119-21meminfo08:10:240
3123899220,22cyclictest20655-21meminfo09:35:220
3123899220,22cyclictest12835-21meminfo07:45:220
3123899220,21cyclictest6815-21meminfo11:55:220
2938822215,5sleep10-21swapper/107:05:021
3123899210,21cyclictest8282-21meminfo10:30:250
3123899210,21cyclictest5523-21meminfo07:25:260
3123899210,21cyclictest31212-21meminfo08:35:250
3123899210,21cyclictest2474-21meminfo08:45:270
3123899210,21cyclictest1339-21meminfo11:40:250
3123899190,19cyclictest9196-21meminfo07:35:220
3123899190,19cyclictest31926-21meminfo11:35:250
3123899190,19cyclictest3181-21meminfo11:45:240
3123899190,19cyclictest2826-21meminfo10:15:260
3123899180,18cyclictest4646-21meminfo10:20:240
3123899180,18cyclictest19549-21meminfo12:30:260
3123999170,6cyclictest0-21swapper/108:45:231
3123899170,17cyclictest31859-21meminfo07:10:260
3123899170,17cyclictest28284-21meminfo11:25:250
3123899170,17cyclictest24293-21meminfo09:45:240
3123899170,17cyclictest18839-21meminfo09:30:240
3123899170,17cyclictest14091-21meminfo12:15:250
3123899170,17cyclictest13732-21meminfo10:45:230
294102171,12sleep029422-21/usr/sbin/munin07:05:150
3123999162,6cyclictest0-21swapper/107:25:211
3123999162,5cyclictest0-21swapper/110:50:211
3123999161,5cyclictest0-21swapper/108:20:181
3123999160,5cyclictest0-21swapper/108:30:201
3123899160,16cyclictest962-21meminfo10:10:230
3123899160,16cyclictest27932-21meminfo09:55:260
3123899160,16cyclictest16665-21meminfo07:55:260
3123999152,7cyclictest0-21swapper/110:05:231
3123899150,15cyclictest6110-21meminfo08:55:250
3123899150,15cyclictest30103-21meminfo11:30:260
3123999143,5cyclictest0-21swapper/109:45:201
3123999143,4cyclictest0-21swapper/112:15:241
3123999142,5cyclictest0-21swapper/109:10:311
3123999141,7cyclictest0-21swapper/109:59:381
3123999141,5cyclictest0-21swapper/111:50:171
3123999141,5cyclictest0-21swapper/111:05:221
3123999140,9cyclictest0-21swapper/107:10:221
3123999140,7cyclictest0-21swapper/110:20:251
3123899140,14cyclictest29389-21meminfo08:30:240
3123999133,4cyclictest0-21swapper/108:50:201
3123999132,9cyclictest0-21swapper/110:15:261
3123999132,4cyclictest0-21swapper/111:20:191
3123999132,4cyclictest0-21swapper/108:05:161
3123999131,4cyclictest0-21swapper/109:15:191
3123999131,4cyclictest0-21swapper/108:40:181
3123999131,4cyclictest0-21swapper/107:50:231
3123999131,2cyclictest0-21swapper/108:15:211
3123999131,2cyclictest0-21swapper/107:55:211
3123899130,13cyclictest26109-21meminfo09:50:260
3123899130,13cyclictest13382-21meminfo09:15:230
3123899130,13cyclictest11567-21meminfo09:10:260
3123999123,5cyclictest0-21swapper/111:30:201
3123999122,6cyclictest0-21swapper/110:35:201
3123999122,6cyclictest0-21swapper/110:30:201
3123999122,5cyclictest0-21swapper/111:11:401
3123999122,4cyclictest0-21swapper/112:35:181
3123999121,5cyclictest0-21swapper/107:15:191
3123999121,4cyclictest0-21swapper/107:40:191
3123899120,12cyclictest31568-21meminfo10:05:240
3123999115,4cyclictest0-21swapper/112:25:191
3123999112,5cyclictest0-21swapper/112:00:281
3123899110,11cyclictest22826-21meminfo11:10:230
3123999102,7cyclictest0-21swapper/111:40:021
3123999101,6cyclictest0-21swapper/108:00:291
3123999100,6cyclictest0-21swapper/108:35:301
312399996,2cyclictest0-21swapper/109:40:231
312399994,3cyclictest0-21swapper/111:55:281
312399994,3cyclictest0-21swapper/109:30:181
312399993,3cyclictest0-21swapper/110:00:211
312399992,5cyclictest0-21swapper/107:50:001
312399992,3cyclictest0-21swapper/112:31:441
312399992,2cyclictest0-21swapper/108:10:241
312399991,5cyclictest0-21swapper/107:20:221
312399991,4cyclictest0-21swapper/112:05:181
312399990,5cyclictest0-21swapper/109:00:341
312399990,4cyclictest0-21swapper/110:40:171
312399985,2cyclictest0-21swapper/110:55:331
312399983,4cyclictest0-21swapper/108:55:221
312399983,3cyclictest0-21swapper/111:00:201
312399982,3cyclictest0-21swapper/109:20:181
312399981,6cyclictest0-21swapper/111:15:221
312399981,4cyclictest0-21swapper/111:35:191
312399981,3cyclictest0-21swapper/112:20:261
312399981,3cyclictest0-21swapper/109:50:181
312399980,7cyclictest10641-21chrt09:08:291
312399980,5cyclictest0-21swapper/107:30:221
312399975,1cyclictest20058-21chrt09:35:141
312399973,3cyclictest0-21swapper/110:10:291
312399972,3cyclictest0-21swapper/112:10:421
312399972,1cyclictest0-21swapper/107:35:201
312399971,4cyclictest0-21swapper/110:26:401
312399971,3cyclictest0-21swapper/111:46:041
312399971,3cyclictest0-21swapper/111:25:231
312399971,2cyclictest0-21swapper/110:45:171
312389970,7cyclictest17372-21meminfo10:55:260
312399965,1cyclictest18017-21chrt09:29:311
312399960,4cyclictest0-21swapper/108:25:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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