You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-02-15 - 11:53
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot0.osadl.org (updated Sat Feb 15, 2025 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6613
"cycles":100000000,6612
"load":"idle",6611
"condition":{6610
"clock":"2300"6608
"family":"x86",6607
"vendor":"Intel",6606
"processor":{6604
"dataset":"2024-01-08T15:38:01+01:00"6602
"origin":"2024-01-08T12:43:22+01:00",6601
"timestamps":{6600
"granularity":"microseconds"6598
4009:57:566596
37,09:57:536595
36,09:57:526594
35,09:57:516593
"maxima":[6592
009:57:166589
0,09:57:166588
0,09:57:166587
0,09:57:166586
0,09:57:166585
0,09:57:166584
0,09:57:166583
0,09:57:166582
0,09:57:166581
0,09:57:166580
0,09:57:166579
0,09:57:166578
0,09:57:166577
0,09:57:166576
0,09:57:166575
0,09:57:166574
0,09:57:166573
0,09:57:166572
0,09:57:166571
0,09:57:166570
0,09:57:166569
0,09:57:166568
0,09:57:166567
0,09:57:166566
0,09:57:166565
0,09:57:166564
0,09:57:166563
0,09:57:166562
0,09:57:166561
0,09:57:166560
0,09:57:166559
0,09:57:166558
0,09:57:166557
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional