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2024-11-09 - 08:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack9slot1.osadl.org (updated Sat Aug 08, 2020 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811150,0rcu_preempt7239-21at-spi-registry09:30:240
811130,0rcu_preempt27309-21kworker/0:109:57:340
811100,0rcu_preempt27743-21ssh11:31:270
811100,0rcu_preempt12081-21ssh11:53:560
811090,0rcu_preempt7260-21gdm-simple-gree11:06:400
811090,0rcu_preempt7260-21gdm-simple-gree10:16:180
811090,0rcu_preempt20555-21ssh10:36:470
811080,0rcu_preempt7260-21gdm-simple-gree09:06:290
811080,0rcu_preempt24557-21ssh12:12:350
811070,0rcu_preempt7260-21gdm-simple-gree10:24:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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