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2025-03-22 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Sat Mar 22, 2025 12:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19142312274,25sleep10-21swapper/11
17052303265,25sleep30-21swapper/33
326612295213,68sleep20-21swapper/22
209599285281,2cyclictest0-21swapper/22
16562247209,25sleep00-21swapper/00
208499232227,3cyclictest505-21dbus-daemon0
209999189185,2cyclictest35-21ksoftirqd/33
208999188182,4cyclictest6645-21perf1
221232570,2sleep30-21swapper/33
313942530,4sleep20-21swapper/22
311762530,4sleep3209999cyclictest3
201692390,2sleep00-21swapper/00
238002350,1sleep00-21swapper/00
73472280,2sleep00-21swapper/00
2099992621,3cyclictest22583-21munin-run3
313362250,3sleep0208499cyclictest0
208999240,12cyclictest269022pmu-power1
269062230,2sleep20-21swapper/22
214242230,1sleep00-21swapper/00
2099992316,4cyclictest25210-21ls3
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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