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2026-05-16 - 12:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Sat May 16, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
197402268238,16sleep10-21swapper/11
212692261224,24sleep00-21swapper/00
2167999260253,5cyclictest26351-21dump-pmu-power2
213832250185,24sleep30-21swapper/33
212082246209,25sleep20-21swapper/22
2167599178173,3cyclictest512-21dbus-daemon1
2168199166162,2cyclictest0-21swapper/33
2167099137131,4cyclictest325-21systemd-journal0
192292720,11sleep219228-21basename2
192292720,11sleep219228-21basename2
40302680,4sleep04032-21aten2_r9power_c0
121572560,1sleep10-21swapper/11
280932530,1sleep30-21swapper/33
44392510,1sleep00-21swapper/00
25352460,3sleep10-21swapper/11
38512360,1sleep00-21swapper/00
221732280,1sleep10-21swapper/11
21675992720,5cyclictest21-21ksoftirqd/11
2167999261,21cyclictest1-21systemd2
2167999241,20cyclictest537-21gdbus2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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