You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-15 - 07:14
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot2.osadl.org (updated Mon Apr 15, 2024 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94572254218,23sleep20-21swapper/22
111012249184,52sleep00-21swapper/00
108762238172,17sleep10-21swapper/11
1136399227221,4cyclictest13284-21munin-run3
109612227189,25sleep30-21swapper/33
1134799156150,3cyclictest0-21swapper/00
1069721550,4sleep31136399cyclictest3
1135899112107,3cyclictest13279-21cron2
113519910499,3cyclictest13303-21grep1
111822570,1sleep20-21swapper/22
7232550,2sleep30-21swapper/33
247522510,4sleep11135199cyclictest1
97832450,1sleep20-21swapper/22
97832450,1sleep20-21swapper/22
272442310,12sleep121-21ksoftirqd/11
1136399286,20cyclictest0-21swapper/33
282882260,3sleep335-21ksoftirqd/33
1136399249,2cyclictest111rcu_preempt3
11363992416,5cyclictest26761-21df3
11358992417,4cyclictest26782-21cpuspeed_turbos2
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional