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2021-10-26 - 22:59

Intel(R) Atom(TM) CPU E640 @ 1.00GHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack9slot4.osadl.org (updated Tue Oct 26, 2021 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175941193160sleep0-21swapper/103:54:331
17832991143cyclictest7522-21sh06:33:440
17832991124cyclictest4145-21dmesg06:25:130
17832991114cyclictest4330-21/usr/sbin/munin08:55:180
17832991113cyclictest22665-21sh08:21:270
17832991113cyclictest18462-21latency_hist06:59:450
17832991108cyclictest0-21swapper/008:49:480
17832991108cyclictest0-21swapper/008:49:480
17832991099cyclictest0-21swapper/005:30:170
17633110964sleep0-21swapper/003:54:350
178329910852cyclictest32386-21/usr/sbin/munin04:40:110
178329910656cyclictest31144-21ssh08:40:300
17832991063cyclictest23865-21sh05:56:110
17832991058cyclictest20200-21needreboot04:00:140
178329910555cyclictest6950irq/18-mmc007:49:460
178329910555cyclictest6950irq/18-mmc007:30:150
17832991054cyclictest74-21mmcqd/009:15:300
17832991053cyclictest6871-21latency_hist05:04:410
178329910513cyclictest20700-21latency_hist05:49:420
17832991043cyclictest74-21mmcqd/007:41:530
17832991038cyclictest0-21swapper/008:39:470
17832991038cyclictest0-21swapper/007:50:250
17832991034cyclictest1632-21diskstats07:35:190
17832991033cyclictest12531-21grep05:20:210
17832991029cyclictest0-21swapper/007:05:150
17832991028cyclictest0-21swapper/008:45:180
17832991024cyclictest19132-21latency_hist05:44:430
17832991019cyclictest13160-21ssh09:14:490
17832991019cyclictest0-21swapper/007:20:130
17832991019cyclictest0-21swapper/007:20:130
178329910055cyclictest6950irq/18-mmc006:05:130
1783299999cyclictest0-21swapper/008:09:590
1783299999cyclictest0-21swapper/004:25:140
1783299999cyclictest0-21swapper/004:10:270
1783299998cyclictest0-21swapper/007:59:470
1783299998cyclictest0-21swapper/007:59:470
1783299998cyclictest0-21swapper/006:50:280
1783299998cyclictest0-21swapper/006:35:140
1783299997cyclictest0-21swapper/009:20:010
17832999959cyclictest74-21mmcqd/005:10:220
17832999953cyclictest0-21swapper/006:49:440
1783299987cyclictest27591-21latency_hist08:34:470
1783299983cyclictest30813-21irqstats04:35:110
1783299978cyclictest0-21swapper/005:19:420
1783299973cyclictest21154-21latency_hist08:19:470
1783299969cyclictest0-21swapper/004:05:160
17832999658cyclictest6950irq/18-mmc007:19:450
1783299958cyclictest21818-21grep05:50:220
1783299955cyclictest6950irq/18-mmc005:35:050
1783299946cyclictest9976-21ssh09:05:560
1783299945cyclictest1510-21latency_hist06:19:440
1783299937cyclictest0-21swapper/008:28:290
1783299937cyclictest0-21swapper/007:04:220
1783299934cyclictest74-21mmcqd/008:09:470
17832999338cyclictest6950irq/18-mmc007:24:510
1783299933cyclictest19271-21latency_hist03:59:390
17832999250cyclictest74-21mmcqd/005:09:080
1783299917cyclictest0-21swapper/004:21:210
1783299909cyclictest0-21swapper/006:00:020
1783299906cyclictest0-21swapper/004:18:570
1783299904cyclictest2559-21ssh06:20:240
1783299898cyclictest0-21swapper/006:10:130
1783299897cyclictest0-21swapper/006:41:560
1783299889cyclictest0-21swapper/004:49:470
1783299888cyclictest0-21swapper/009:00:180
1783299877cyclictest0-21swapper/007:12:220
1783299877cyclictest0-21swapper/004:56:230
1783299867cyclictest0-21swapper/004:45:180
17832998634cyclictest0-21swapper/008:01:110
1783299849cyclictest0-21swapper/004:30:130
1783299847cyclictest0-21swapper/005:25:220
1783299847cyclictest0-21swapper/005:25:220
22250830irq/18-spi_topc191ksoftirqd/106:10:131
1783399758cyclictest0-21swapper/106:39:491
22250690irq/18-spi_topc0-21swapper/109:09:511
1783399697cyclictest0-21swapper/107:45:151
6950680irq/18-mmc0191ksoftirqd/106:09:201
1783399688cyclictest0-21swapper/105:10:191
22250670irq/18-spi_topc0-21swapper/105:20:511
1783399678cyclictest0-21swapper/106:30:411
1783399669cyclictest0-21swapper/106:35:401
1783399668cyclictest0-21swapper/109:15:231
17833996615cyclictest0-21swapper/106:52:501
1783399657cyclictest0-21swapper/109:08:431
1783399657cyclictest0-21swapper/107:34:051
1783399657cyclictest0-21swapper/105:57:361
1783399656cyclictest0-21swapper/105:17:411
1783399648cyclictest0-21swapper/106:19:181
1783399648cyclictest0-21swapper/104:45:231
1783399648cyclictest0-21swapper/104:15:171
1783399647cyclictest0-21swapper/104:40:091
1783399646cyclictest0-21swapper/105:08:111
17833996424cyclictest0-21swapper/108:47:191
22250630irq/18-spi_topc0-21swapper/106:20:141
1783399638cyclictest0-21swapper/107:13:011
1783399637cyclictest0-21swapper/108:40:201
1783399637cyclictest0-21swapper/107:58:201
1783399637cyclictest0-21swapper/107:58:201
1783399636cyclictest0-21swapper/107:39:201
1783399636cyclictest0-21swapper/106:55:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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