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2025-04-30 - 09:52

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #9, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack9slot4s (updated Wed Apr 30, 2025 00:59:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285639912231201,19cyclictest0-21swapper/119:30:041
28562995691,564cyclictest30908-21fschecks_time19:30:030
274002567519,32sleep00-21swapper/019:20:250
282502462418,29sleep10-21swapper/119:22:171
69362670,6sleep02856299cyclictest21:15:270
36552610,7sleep02856299cyclictest00:00:150
146522540,8sleep12856399cyclictest00:30:131
269752470,8sleep12856399cyclictest23:35:231
2856399447,4cyclictest22-21ksoftirqd/122:23:041
2856399445,4cyclictest81rcu_preempt23:45:261
2856399443,10cyclictest0-21swapper/121:55:201
2856399433,10cyclictest0-21swapper/122:25:291
28563994317,6cyclictest22-21ksoftirqd/123:15:311
28563994314,6cyclictest22-21ksoftirqd/120:36:171
2856399426,6cyclictest22-21ksoftirqd/120:12:091
2856399426,6cyclictest22-21ksoftirqd/120:12:091
2856399422,9cyclictest0-21swapper/119:50:241
28563994216,5cyclictest22-21ksoftirqd/120:40:311
28563994215,6cyclictest22-21ksoftirqd/100:10:321
28563994213,8cyclictest22-21ksoftirqd/122:07:191
28563994213,6cyclictest22-21ksoftirqd/119:55:061
28563994213,5cyclictest22-21ksoftirqd/100:47:371
28563994212,4cyclictest22-21ksoftirqd/119:41:231
28563994210,4cyclictest81rcu_preempt20:59:401
28563994210,4cyclictest22-21ksoftirqd/123:11:271
28563994210,4cyclictest22-21ksoftirqd/122:15:491
2856399419,3cyclictest22-21ksoftirqd/121:28:461
2856399418,5cyclictest3020-21runrttasks20:01:551
28563994119,8cyclictest22-21ksoftirqd/123:44:461
28563994119,8cyclictest22-21ksoftirqd/100:37:071
28563994117,5cyclictest22-21ksoftirqd/121:50:171
28563994116,5cyclictest22-21ksoftirqd/123:59:091
28563994115,5cyclictest22-21ksoftirqd/100:09:361
28563994114,6cyclictest22-21ksoftirqd/123:29:271
28563994112,4cyclictest22-21ksoftirqd/100:25:201
28563994111,4cyclictest22-21ksoftirqd/120:50:151
28563994111,4cyclictest22-21ksoftirqd/120:31:031
28563994111,3cyclictest22-21ksoftirqd/121:48:441
28563994110,4cyclictest22-21ksoftirqd/119:48:011
2856399406,6cyclictest22-21ksoftirqd/120:26:411
2856399403,11cyclictest0-21swapper/122:01:251
28563994020,8cyclictest22-21ksoftirqd/100:17:161
28563994015,5cyclictest22-21ksoftirqd/122:45:281
28563994014,6cyclictest22-21ksoftirqd/121:15:131
28563994011,3cyclictest22-21ksoftirqd/123:08:351
28563994011,3cyclictest22-21ksoftirqd/123:08:351
28563994011,3cyclictest22-21ksoftirqd/121:32:181
28563994010,5cyclictest22-21ksoftirqd/100:21:361
28563994010,4cyclictest22-21ksoftirqd/122:50:541
28563994010,4cyclictest22-21ksoftirqd/122:12:371
2856399399,4cyclictest22-21ksoftirqd/122:31:461
2856399395,5cyclictest13972-21ntpq23:00:261
2856399395,5cyclictest13972-21ntpq23:00:251
28563993922,4cyclictest22-21ksoftirqd/121:20:311
28563993914,6cyclictest22-21ksoftirqd/121:00:541
28563993914,6cyclictest22-21ksoftirqd/119:36:191
28563993914,5cyclictest22-21ksoftirqd/120:16:381
28563993914,5cyclictest22-21ksoftirqd/100:00:201
28563993913,5cyclictest22-21ksoftirqd/121:14:431
28563993912,8cyclictest22-21ksoftirqd/121:05:171
28563993910,9cyclictest22-21ksoftirqd/123:21:261
28563993910,4cyclictest22-21ksoftirqd/122:43:521
28563993910,4cyclictest22-21ksoftirqd/121:36:301
28563993910,4cyclictest22-21ksoftirqd/120:47:221
28563993814,6cyclictest22-21ksoftirqd/120:06:321
28563993813,6cyclictest22-21ksoftirqd/122:35:141
28563993812,5cyclictest22-21ksoftirqd/123:50:501
2856399378,4cyclictest81rcu_preempt21:40:131
28563993723,4cyclictest22-21ksoftirqd/123:33:101
28563993713,6cyclictest22-21ksoftirqd/122:58:281
313122361,5sleep031325-21hddtemp_smartct20:55:230
28563993618,4cyclictest22-21ksoftirqd/119:26:471
28563993618,4cyclictest22-21ksoftirqd/100:53:561
2856299369,12cyclictest6204-21gdbus00:11:070
2856299362,11cyclictest81rcu_preempt19:58:370
2856399352,8cyclictest0-21swapper/120:20:131
28563993511,4cyclictest22-21ksoftirqd/100:41:201
217282351,30sleep06204-21gdbus00:47:090
28562993410,11cyclictest0-21swapper/000:50:550
176802341,4sleep017785-21wget20:20:130
2856299337,13cyclictest1930-21cpuspeed_turbos22:30:140
2856299331,28cyclictest13987-21cut21:35:170
170732331,9sleep00-21swapper/021:44:320
2856299326,12cyclictest7898-21fschecks_count22:45:180
2856299323,4cyclictest81rcu_preempt23:55:180
2856299321,4cyclictest81rcu_preempt20:37:260
2856299321,4cyclictest81rcu_preempt00:22:170
28562993213,16cyclictest20105-21sh00:45:000
2856299321,17cyclictest19586-21fschecks_time21:50:170
2856299321,13cyclictest0-21swapper/023:12:320
2856299321,13cyclictest0-21swapper/023:03:100
2856299321,13cyclictest0-21swapper/023:03:100
2856299317,12cyclictest12251-21irqstats21:30:230
28562993121,5cyclictest32440-21wget22:25:160
2856299311,4cyclictest81rcu_preempt23:49:070
2856299311,4cyclictest81rcu_preempt23:38:030
2856299311,4cyclictest81rcu_preempt23:19:020
2856299311,4cyclictest81rcu_preempt21:29:100
2856299311,4cyclictest81rcu_preempt20:53:570
2856299311,4cyclictest81rcu_preempt20:40:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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