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2019-07-22 - 07:33

Intel(R) Celeron(R) CPU G1620 @ 2.70GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #9, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack9slot5.osadl.org (updated Mon Jul 22, 2019 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24332450,0sleep00-21swapper/020:58:550
207599450,38rtkit-daemon0-21swapper/119:05:141
184442450,1sleep00-21swapper/023:13:590
171372450,1sleep117134-21x2golistsession22:24:591
160262440,1sleep10-21swapper/121:14:091
222562420,0sleep10-21swapper/122:52:391
199762420,0sleep00-21swapper/022:27:280
89842400,1sleep10-21swapper/123:29:561
132242400,0sleep00-21swapper/022:45:330
287892390,0sleep00-21swapper/021:46:300
230662390,0sleep00-21swapper/019:55:590
324362380,0sleep132435-21irqstats_122:59:561
192772273,3sleep00-21swapper/019:05:220
147012190,0sleep00-21swapper/021:12:490
2099599150,14cyclictest8848-21/usr/sbin/munin23:29:550
2099699140,13cyclictest5040-21sh22:16:161
20996991310,3cyclictest0-21swapper/122:30:361
2099699130,13cyclictest0-21swapper/122:40:161
20995991313,0cyclictest0-21swapper/000:27:050
2099599130,0cyclictest0-21swapper/022:37:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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