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2022-01-26 - 13:13

Intel(R) Celeron(R) CPU G1620 @ 2.70GHz, Linux 5.4.17-rt9 (Profile)

Latency plot of system in rack #9, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack9slot5.osadl.org (updated Wed Jan 26, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1160821000,0sleep111607-21x2golistsession21:50:201
211312980,0sleep121130-21x2gosqlitewrapp21:57:471
86602480,1sleep08658-21ssh23:44:110
41992430,0sleep10-21swapper/118:58:311
135402430,0sleep113541-21x2gopath19:09:371
151632420,0sleep00-21swapper/023:49:060
34052400,0sleep10-21swapper/120:27:091
229572227,10sleep00-21swapper/018:39:060
250032218,9sleep10-21swapper/118:41:211
26026991512,2cyclictest15422-21x2gosqlitewrapp00:12:591
2602699150,1cyclictest11509-21x2golistsession19:53:581
26025991513,1cyclictest4000-21ssh21:44:390
284982140,0sleep00-21swapper/023:12:380
264599140,1rtkit-daemon2644-21rtkit-daemon19:20:481
264599140,1rtkit-daemon2644-21rtkit-daemon00:01:211
264599140,1rtkit-daemon2644-21rtkit-daemon00:01:211
262322140,0sleep10-21swapper/118:44:011
2602699140,13cyclictest0-21swapper/122:49:581
284622130,0sleep10-21swapper/120:53:411
26026991313,0cyclictest0-21swapper/121:09:081
2602699130,13cyclictest0-21swapper/123:55:081
2602699130,13cyclictest0-21swapper/123:09:381
2602699130,13cyclictest0-21swapper/122:44:381
2602699130,13cyclictest0-21swapper/122:25:281
26025991313,0cyclictest0-21swapper/022:23:390
26025991313,0cyclictest0-21swapper/021:25:090
26025991312,0cyclictest0-21swapper/021:05:590
26025991311,1cyclictest9036-21sh22:58:490
2602599130,13cyclictest0-21swapper/020:54:390
2602599130,0cyclictest0-21swapper/022:53:490
2602599130,0cyclictest0-21swapper/022:09:290
2602599130,0cyclictest0-21swapper/020:45:090
26026991212,0cyclictest0-21swapper/123:44:481
26026991212,0cyclictest0-21swapper/123:32:181
26026991212,0cyclictest0-21swapper/123:14:181
26026991212,0cyclictest0-21swapper/123:04:581
26026991212,0cyclictest0-21swapper/122:08:481
26026991212,0cyclictest0-21swapper/121:30:481
26026991212,0cyclictest0-21swapper/121:06:381
26026991212,0cyclictest0-21swapper/120:55:381
26026991212,0cyclictest0-21swapper/120:40:381
26026991212,0cyclictest0-21swapper/119:43:471
2602699120,0cyclictest0-21swapper/123:34:481
2602699120,0cyclictest0-21swapper/119:05:171
26025991212,0cyclictest0-21swapper/023:57:500
26025991212,0cyclictest0-21swapper/022:06:390
26025991212,0cyclictest0-21swapper/021:14:090
26025991212,0cyclictest0-21swapper/019:35:590
26025991212,0cyclictest0-21swapper/000:05:400
2602599120,12cyclictest0-21swapper/022:43:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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