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2021-10-16 - 13:41

Intel(R) Core(TM) i3-4330T CPU @ 3.00GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack9slot6.osadl.org (updated Sat Oct 16, 2021 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31558210951,29sleep30-21swapper/319:09:513
31257210054,29sleep10-21swapper/119:05:561
3126127151,16sleep00-21swapper/019:05:590
3119826952,8sleep20-21swapper/219:05:252
290472670,1sleep20-21swapper/221:30:002
3186799220,20cyclictest0-21swapper/321:01:503
3186799210,2cyclictest0-21swapper/322:52:393
31866992015,3cyclictest25223-21/usr/sbin/munin22:35:152
31866992014,4cyclictest17466-21/usr/sbin/munin22:15:192
31865992018,1cyclictest0-21swapper/100:00:161
31864992018,1cyclictest30664-21fw_conntrack00:00:160
3186699190,17cyclictest0-21swapper/222:45:252
3186599190,17cyclictest0-21swapper/119:40:211
3186799180,17cyclictest0-21swapper/322:35:213
3186799180,17cyclictest0-21swapper/322:10:143
31866991815,2cyclictest30665-21cat00:00:162
3186599180,2cyclictest0-21swapper/122:40:181
3186499180,16cyclictest0-21swapper/020:25:230
3186799170,2cyclictest0-21swapper/323:05:193
31866991712,3cyclictest16618-21gltestperf21:00:182
3186699170,2cyclictest0-21swapper/220:45:152
31865991715,1cyclictest0-21swapper/122:35:151
3186499170,16cyclictest0-21swapper/022:10:140
3186499170,15cyclictest0-21swapper/020:50:170
3186799160,14cyclictest0-21swapper/321:55:163
3186799160,13cyclictest5333-21perf21:50:003
3186799160,13cyclictest5333-21perf21:50:003
31865991511,3cyclictest0-21swapper/122:30:391
3186599150,13cyclictest0-21swapper/100:35:001
31867991412,1cyclictest0-21swapper/323:56:493
31867991412,1cyclictest0-21swapper/322:55:183
31867991412,1cyclictest0-21swapper/322:30:583
31867991412,1cyclictest0-21swapper/322:26:593
31867991412,1cyclictest0-21swapper/322:24:283
31867991412,1cyclictest0-21swapper/322:02:083
31867991412,1cyclictest0-21swapper/321:30:083
31867991412,1cyclictest0-21swapper/320:46:473
31867991412,1cyclictest0-21swapper/319:40:473
31867991412,1cyclictest0-21swapper/319:31:273
31867991412,1cyclictest0-21swapper/319:21:373
31867991412,1cyclictest0-21swapper/319:18:373
31867991412,1cyclictest0-21swapper/300:35:593
31866991412,1cyclictest0-21swapper/223:33:182
31866991412,1cyclictest0-21swapper/223:25:492
31866991412,1cyclictest0-21swapper/222:58:582
31866991412,1cyclictest0-21swapper/222:07:482
31866991412,1cyclictest0-21swapper/219:41:372
31866991412,1cyclictest0-21swapper/200:27:192
3186699140,2cyclictest0-21swapper/222:40:182
31865991412,1cyclictest0-21swapper/121:35:381
31865991412,1cyclictest0-21swapper/119:36:171
31865991412,1cyclictest0-21swapper/119:29:471
31865991412,1cyclictest0-21swapper/100:37:291
3186599140,2cyclictest0-21swapper/121:50:161
3186599140,12cyclictest8476-21perf00:25:001
3186599140,12cyclictest0-21swapper/123:35:001
3186599140,12cyclictest0-21swapper/121:20:001
3186599140,12cyclictest0-21swapper/100:19:551
31864991412,1cyclictest0-21swapper/023:55:280
31864991412,1cyclictest0-21swapper/023:12:280
31864991412,1cyclictest0-21swapper/021:56:180
31864991412,1cyclictest0-21swapper/021:03:070
31864991412,1cyclictest0-21swapper/019:23:370
3186499140,1cyclictest0-21swapper/021:29:180
3186499140,1cyclictest0-21swapper/020:40:180
3186499140,1cyclictest0-21swapper/000:25:090
3186499140,13cyclictest0-21swapper/023:52:090
3186499140,13cyclictest0-21swapper/023:38:090
3186499140,13cyclictest0-21swapper/022:42:380
3186499140,13cyclictest0-21swapper/022:30:590
3186499140,13cyclictest0-21swapper/022:06:080
3186499140,13cyclictest0-21swapper/020:32:080
3186499140,13cyclictest0-21swapper/020:10:370
3186499140,13cyclictest0-21swapper/019:26:570
3186499140,13cyclictest0-21swapper/019:17:370
3186499140,13cyclictest0-21swapper/000:34:490
3186499140,13cyclictest0-21swapper/000:18:390
3186499140,13cyclictest0-21swapper/000:08:490
31867991311,1cyclictest0-21swapper/323:21:093
31867991311,1cyclictest0-21swapper/323:21:083
31867991311,1cyclictest0-21swapper/322:46:383
31867991311,1cyclictest0-21swapper/320:41:183
31867991311,1cyclictest0-21swapper/319:55:073
31867991311,1cyclictest0-21swapper/300:32:493
31867991311,1cyclictest0-21swapper/300:16:383
31867991311,1cyclictest0-21swapper/300:00:093
3186799130,11cyclictest0-21swapper/319:29:013
31866991311,1cyclictest0-21swapper/223:01:482
31866991311,1cyclictest0-21swapper/221:50:582
31866991311,1cyclictest0-21swapper/221:24:072
31866991311,1cyclictest0-21swapper/220:12:272
31866991311,1cyclictest0-21swapper/219:29:072
31866991311,1cyclictest0-21swapper/200:20:492
31866991311,1cyclictest0-21swapper/200:14:192
31865991311,1cyclictest0-21swapper/123:19:191
31865991311,1cyclictest0-21swapper/122:53:481
31865991311,1cyclictest0-21swapper/122:05:491
31865991311,1cyclictest0-21swapper/121:13:371
31865991311,1cyclictest0-21swapper/120:56:281
31865991311,1cyclictest0-21swapper/119:50:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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