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2023-02-06 - 13:27

x86 Intel Core i3-4330T @3000 MHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack9slot6.osadl.org (updated Mon Feb 06, 2023 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248632142105sleep30-21swapper/319:05:033
266152137126sleep10-21swapper/119:06:201
26678213587sleep20-21swapper/219:07:092
26857210796sleep00-21swapper/019:09:280
27191994240cyclictest2166-21df_inode20:35:132
27192993533cyclictest0-21swapper/300:00:213
27192993418cyclictest0-21swapper/323:00:223
27189993317cyclictest0-21swapper/022:00:170
27189993317cyclictest0-21swapper/020:50:140
27191993231cyclictest0-21swapper/200:12:482
27190992928cyclictest3186850kworker/u8:123:42:001
27190992928cyclictest3186850kworker/u8:123:39:591
27190992928cyclictest3186850kworker/u8:119:22:001
27192992818cyclictest0-21swapper/300:35:213
27192992812cyclictest0-21swapper/323:10:133
27190992827cyclictest3186850kworker/u8:120:29:001
27190992827cyclictest2528150kworker/u8:000:17:001
27190992726cyclictest2639750kworker/u8:022:09:001
27190992624cyclictest2639750kworker/u8:022:19:001
27189992611cyclictest0-21swapper/021:25:260
2719099252cyclictest3186850kworker/u8:119:15:001
2719099252cyclictest2639750kworker/u8:022:44:001
2719099252cyclictest2639750kworker/u8:022:25:001
2719099252cyclictest25281-21kworker/u8:000:13:011
27190992524cyclictest26397-21kworker/u8:022:48:591
27190992523cyclictest26397-21kworker/u8:021:31:591
27191992423cyclictest71650irq/33-p4p1-rx-00:09:562
27190992423cyclictest31868-21kworker/u8:119:20:001
2719099241cyclictest3186850kworker/u8:121:21:591
2719099241cyclictest3186850kworker/u8:121:02:001
2719099241cyclictest3186850kworker/u8:120:50:001
2719099241cyclictest3186850kworker/u8:120:09:001
2719099241cyclictest31868-21kworker/u8:123:28:011
2719099241cyclictest31868-21kworker/u8:123:28:001
2719099241cyclictest2639750kworker/u8:021:55:001
2719099241cyclictest2528150kworker/u8:000:08:001
27190992418cyclictest0-21swapper/120:00:251
27191992322cyclictest0-21swapper/223:35:232
27191992320cyclictest21390-21df_inode23:40:142
27191992319cyclictest11824-21memory20:55:182
27190992320cyclictest0-21swapper/121:40:151
27190992319cyclictest0-21swapper/122:25:181
27190992318cyclictest0-21swapper/123:20:371
27189992317cyclictest0-21swapper/019:35:150
27192992219cyclictest0-21swapper/319:30:153
27191992218cyclictest0-21swapper/221:25:172
27190992220cyclictest17457-21awk21:09:591
2718999226cyclictest0-21swapper/021:40:150
27192992120cyclictest0-21swapper/322:15:213
27192992119cyclictest0-21swapper/322:10:123
2719199215cyclictest0-21swapper/220:10:172
27191992119cyclictest0-21swapper/223:10:172
27191992118cyclictest0-21swapper/220:50:152
27191992117cyclictest5791-21ntp_states19:30:182
27189992119cyclictest495-21in:imjournal19:20:010
27189992111cyclictest0-21swapper/021:30:190
2719299205cyclictest0-21swapper/300:15:243
2719299204cyclictest0-21swapper/322:00:123
27192992018cyclictest13497-21idleruntime-cro19:49:593
27192992018cyclictest0-21swapper/322:05:143
27191992018cyclictest0-21swapper/222:15:202
27191992018cyclictest0-21swapper/221:00:212
2719099204cyclictest0-21swapper/100:20:231
27190992018cyclictest0-21swapper/123:50:191
27190992018cyclictest0-21swapper/123:10:231
27190992018cyclictest0-21swapper/121:55:191
27190992018cyclictest0-21swapper/120:40:161
27189992017cyclictest0-21swapper/022:15:260
27189992015cyclictest0-21swapper/023:10:130
27192991917cyclictest0-21swapper/319:50:243
2719099194cyclictest0-21swapper/121:45:151
2719099194cyclictest0-21swapper/120:10:191
27190991918cyclictest0-21swapper/100:00:261
27189991915cyclictest2021-21munin-run00:10:000
27192991816cyclictest0-21swapper/321:10:253
27192991816cyclictest0-21swapper/320:50:143
27192991810cyclictest0-21swapper/319:55:213
27191991816cyclictest0-21swapper/223:45:202
27191991816cyclictest0-21swapper/200:29:592
2719099187cyclictest0-21swapper/120:15:201
27189991817cyclictest495-21in:imjournal23:20:000
27189991814cyclictest0-21swapper/021:55:000
27192991715cyclictest0-21swapper/323:25:193
27192991715cyclictest0-21swapper/323:25:193
27192991715cyclictest0-21swapper/321:30:183
27192991714cyclictest0-21swapper/322:20:143
27192991710cyclictest0-21swapper/322:30:223
27191991716cyclictest71650irq/33-p4p1-rx-23:20:002
27191991715cyclictest30072-21ntp_states19:15:012
27191991715cyclictest0-21swapper/200:20:172
27190991715cyclictest495-21in:imjournal20:59:591
27189991715cyclictest0-21swapper/023:30:160
27189991714cyclictest0-21swapper/000:30:000
27189991713cyclictest23026-21latency_hist23:45:010
222098172rtkit-daemon2219-21rtkit-daemon22:40:232
222098172rtkit-daemon2219-21rtkit-daemon21:05:122
27192991612cyclictest0-21swapper/321:05:003
2719199164cyclictest0-21swapper/221:10:152
27191991614cyclictest0-21swapper/222:00:172
27191991614cyclictest0-21swapper/221:30:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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