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2023-06-01 - 17:07

x86 Intel Core i3-4330T @3000 MHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack9slot6.osadl.org (updated Thu Jun 01, 2023 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322162175127sleep20-21swapper/207:06:272
324742150138sleep30-21swapper/307:09:463
324222146134sleep10-21swapper/107:09:071
32271210694sleep00-21swapper/007:07:090
319993534cyclictest0-21swapper/310:45:253
318993533cyclictest0-21swapper/207:35:272
318993418cyclictest0-21swapper/210:35:322
318992928cyclictest0-21swapper/210:47:002
318992927cyclictest0-21swapper/209:14:002
318992827cyclictest0-21swapper/212:17:002
318992827cyclictest0-21swapper/208:13:592
318992827cyclictest0-21swapper/208:00:592
318992827cyclictest0-21swapper/207:54:002
318992812cyclictest0-21swapper/209:20:402
319992718cyclictest0-21swapper/312:15:003
31899273cyclictest0-21swapper/211:49:002
31899272cyclictest0-21swapper/211:50:592
318992726cyclictest0-21swapper/212:06:002
318992726cyclictest0-21swapper/210:33:002
318992725cyclictest0-21swapper/210:10:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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