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2022-05-26 - 19:04

x86 Intel Core i3-4330T @3000 MHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack9slot6.osadl.org (updated Fri May 20, 2022 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76312171133sleep10-21swapper/119:08:201
57312130119sleep30-21swapper/319:05:063
75172115104sleep20-21swapper/219:06:522
7610211081sleep00-21swapper/019:08:030
8051993532cyclictest0-21swapper/122:35:141
8052992827cyclictest2508550kworker/u8:122:44:592
8052992423cyclictest450-21rngd20:57:002
8052992423cyclictest450-21rngd20:35:002
8052992423cyclictest450-21rngd19:20:592
8052992423cyclictest450-21rngd19:20:592
8051992421cyclictest0-21swapper/123:00:161
8052992322cyclictest0-21swapper/222:05:592
8052992322cyclictest0-21swapper/221:31:002
8052992322cyclictest0-21swapper/221:28:002
8052992322cyclictest0-21swapper/221:12:592
8052992322cyclictest0-21swapper/220:36:002
8052992322cyclictest0-21swapper/219:56:002
8052992322cyclictest0-21swapper/219:46:002
8052992322cyclictest0-21swapper/219:39:002
8052992322cyclictest0-21swapper/219:34:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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