You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-12-04 - 06:58
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack9slot6.osadl.org (updated Mon Dec 04, 2023 00:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25967215087sleep20-21swapper/219:05:342
26092212387sleep10-21swapper/119:07:101
26229212185sleep30-21swapper/319:08:563
26300210881sleep00-21swapper/019:09:500
2660399462cyclictest0-21swapper/120:35:291
26605993519cyclictest0-21swapper/319:45:263
26605993519cyclictest0-21swapper/319:45:253
26605993432cyclictest0-21swapper/320:00:243
26605993418cyclictest0-21swapper/321:30:223
26605993418cyclictest0-21swapper/321:15:263
26605993418cyclictest0-21swapper/320:15:293
26604993418cyclictest0-21swapper/220:20:162
26604993418cyclictest0-21swapper/219:15:232
26603993418cyclictest0-21swapper/120:20:261
26605993318cyclictest0-21swapper/320:30:253
26602993317cyclictest0-21swapper/021:40:270
26602993317cyclictest0-21swapper/021:30:210
26602993317cyclictest0-21swapper/019:15:230
26602993217cyclictest0-21swapper/020:50:200
26602993217cyclictest0-21swapper/020:20:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional