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2025-02-17 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack9slot6.osadl.org (updated Mon Feb 17, 2025 12:54:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3814:12:505033
36,14:12:125032
38,14:12:125031
24,14:12:125030
014:12:125026
0,14:12:125025
0,14:12:125024
0,14:12:125023
0,14:12:125022
0,14:12:125021
0,14:12:125020
0,14:12:125019
0,14:12:125018
0,14:12:125017
0,14:12:125016
0,14:12:125015
0,14:12:125014
0,14:12:125013
0,14:12:125012
0,14:12:125011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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