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2023-06-11 - 03:51

x86 Intel Core i3-4330T @3000 MHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Sun Jun 11, 2023 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
315452175163sleep20-21swapper/219:07:072
315152173161sleep30-21swapper/319:06:443
31641213599sleep10-21swapper/119:08:221
31463210997sleep00-21swapper/019:06:060
32054993432cyclictest0-21swapper/000:25:210
32054993331cyclictest0-21swapper/019:30:220
3205699312cyclictest0-21swapper/220:40:252
32057992818cyclictest0-21swapper/300:05:363
32054992717cyclictest0-21swapper/019:35:180
32057992522cyclictest0-21swapper/323:35:223
32057992522cyclictest0-21swapper/300:20:223
32056992422cyclictest3158-21diskstats19:15:222
32057992320cyclictest0-21swapper/322:10:183
32057992318cyclictest0-21swapper/319:30:223
32056992320cyclictest488-21in:imjournal20:50:002
32056992320cyclictest488-21in:imjournal20:49:592
32057992220cyclictest0-21swapper/321:50:243
32057992220cyclictest0-21swapper/321:25:293
32056992218cyclictest0-21swapper/219:10:382
32055992220cyclictest0-21swapper/123:50:201
32057992119cyclictest0-21swapper/322:35:223
32055992118cyclictest0-21swapper/119:40:261
32057992018cyclictest0-21swapper/323:00:293
32056992018cyclictest0-21swapper/220:25:172
32055992018cyclictest0-21swapper/121:30:241
32055992018cyclictest0-21swapper/119:30:221
32054992017cyclictest0-21swapper/000:00:270
32057991917cyclictest0-21swapper/322:20:293
32057991917cyclictest0-21swapper/320:25:153
32056991918cyclictest26236-21unixbench-2d21:15:332
32054991917cyclictest0-21swapper/021:30:250
32054991917cyclictest0-21swapper/019:15:260
32054991917cyclictest0-21swapper/000:10:210
32054991912cyclictest0-21swapper/022:30:290
32057991817cyclictest0-21swapper/300:05:003
32057991815cyclictest0-21swapper/319:35:163
32056991816cyclictest0-21swapper/200:15:252
32054991817cyclictest0-21swapper/021:05:190
3205799177cyclictest0-21swapper/322:49:593
3205799174cyclictest0-21swapper/319:19:483
32057991715cyclictest0-21swapper/323:15:193
3205699172cyclictest0-21swapper/222:00:352
32056991716cyclictest17954-21aten_r9power_po21:00:162
32056991715cyclictest12494-21munin-run22:00:002
32056991715cyclictest0-21swapper/200:05:292
3205499175cyclictest0-21swapper/020:35:220
32054991716cyclictest0-21swapper/022:20:290
32054991716cyclictest0-21swapper/019:25:230
32054991714cyclictest0-21swapper/021:19:590
32054991713cyclictest7959-21crond21:50:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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