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2024-12-11 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Wed Dec 11, 2024 12:53:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3819:49:415033
36,19:49:035032
38,19:49:035031
24,19:49:035030
019:49:035026
0,19:49:035025
0,19:49:035024
0,19:49:035023
0,19:49:035022
0,19:49:035021
0,19:49:035020
0,19:49:035019
0,19:49:035018
0,19:49:035017
0,19:49:035016
0,19:49:035015
0,19:49:035014
0,19:49:035013
0,19:49:035012
0,19:49:035011
0,19:49:035010
0,19:49:035009
0,19:49:035008
0,19:49:035007
0,19:49:035006
0,19:49:035005
0,19:49:035004
0,19:49:035003
0,19:49:035002
0,19:49:035001
0,19:49:035000
0,19:49:034999
0,19:49:034998
0,19:49:034997
0,19:49:034996
0,19:49:034995
0,19:49:034994
0,19:49:034993
0,19:49:034992
0,19:49:034991
0,19:49:034990
0,19:49:034989
0,19:49:034988
0,19:49:034987
0,19:49:034986
0,19:49:034985
0,19:49:034984
0,19:49:034983
0,19:49:034982
0,19:49:034981
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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