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2021-01-24 - 14:26

Intel(R) Core(TM) i3-4330T CPU @ 3.00GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Sun Jan 24, 2021 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21457211254,30sleep10-21swapper/107:09:171
19539210252,28sleep30-21swapper/307:05:033
81012860,1sleep30-21swapper/311:40:173
2119828152,8sleep20-21swapper/207:05:582
230242790,1sleep30-21swapper/309:45:053
2144427053,13sleep00-21swapper/007:09:080
112442550,1sleep00-21swapper/010:30:130
2179599212,16cyclictest0-21swapper/208:55:072
2179399210,17cyclictest0-21swapper/010:35:120
2179599202,1cyclictest0-21swapper/208:10:082
2179599201,18cyclictest0-21swapper/209:45:082
2179499200,18cyclictest0-21swapper/110:35:151
2179499200,17cyclictest0-21swapper/108:55:061
21796991914,3cyclictest29004-21munin-run10:00:003
2179699190,17cyclictest506-21in:imjournal08:30:003
2179599191,16cyclictest0-21swapper/210:45:072
21796991814,3cyclictest5707-21fw_conntrack09:05:093
2179699180,16cyclictest0-21swapper/309:25:073
2179599180,17cyclictest0-21swapper/210:35:092
21793991813,2cyclictest506-21in:imjournal10:00:000
21796991712,3cyclictest9837-21turbostat.cron10:30:013
21796991712,3cyclictest0-21swapper/309:00:103
21793991712,4cyclictest506-21in:imjournal07:59:590
21793991712,2cyclictest506-21in:imjournal12:40:000
2179399170,1cyclictest0-21swapper/007:35:080
2179399170,15cyclictest0-21swapper/008:25:160
21796991612,3cyclictest0-21swapper/309:35:503
21796991612,2cyclictest21259-21dump-pmu-power08:25:003
21794991611,3cyclictest29000-21dump-pmu-power10:00:001
21793991612,1cyclictest0-21swapper/011:50:110
21793991612,1cyclictest0-21swapper/011:26:510
21793991612,1cyclictest0-21swapper/011:17:510
21793991612,1cyclictest0-21swapper/011:08:010
21793991612,1cyclictest0-21swapper/011:04:300
21793991612,1cyclictest0-21swapper/009:52:400
21793991612,1cyclictest0-21swapper/009:45:500
21793991612,1cyclictest0-21swapper/009:21:300
21793991610,2cyclictest506-21in:imjournal08:54:320
2179399160,1cyclictest0-21swapper/012:26:010
2179399160,1cyclictest0-21swapper/010:19:300
2179399160,13cyclictest0-21swapper/012:21:510
2179399160,13cyclictest0-21swapper/011:11:300
21796991513,1cyclictest0-21swapper/308:35:083
21796991510,3cyclictest30636-21munin-run08:50:003
2179699150,13cyclictest0-21swapper/311:50:053
21793991511,1cyclictest0-21swapper/010:27:400
21793991511,1cyclictest0-21swapper/010:21:000
21793991511,1cyclictest0-21swapper/009:40:300
21793991511,1cyclictest0-21swapper/009:26:200
21793991511,1cyclictest0-21swapper/008:36:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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