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2022-06-29 - 16:03

x86 Intel Core i3-4330T @3000 MHz, Linux 3.18.11-rt7 (Profile)

Latency plot of system in rack #9, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Wed Jun 29, 2022 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
219112139128sleep10-21swapper/107:05:301
221372138127sleep30-21swapper/307:08:253
219442116105sleep20-21swapper/207:05:552
21972211182sleep00-21swapper/007:06:180
22553993734cyclictest0-21swapper/207:10:042
22552993734cyclictest0-21swapper/111:45:191
22551993432cyclictest0-21swapper/008:30:150
22552993118cyclictest0-21swapper/109:30:021
22554992917cyclictest0-21swapper/309:15:223
22554992610cyclictest0-21swapper/307:30:123
22554992519cyclictest0-21swapper/310:05:223
22553992522cyclictest27589-21ls07:20:002
22552992521cyclictest0-21swapper/112:00:201
2255299248cyclictest0-21swapper/112:05:111
22554992319cyclictest0-21swapper/311:25:193
22554992318cyclictest0-21swapper/308:30:133
22553992321cyclictest498-21in:imjournal08:00:012
22553992320cyclictest0-21swapper/210:35:162
22552992320cyclictest0-21swapper/109:20:171
22554992221cyclictest0-21swapper/308:35:153
2255199226cyclictest0-21swapper/009:10:230
22554992119cyclictest0-21swapper/311:55:173
22554992117cyclictest0-21swapper/309:05:123
22553992120cyclictest0-21swapper/211:55:152
2255299215cyclictest0-21swapper/108:10:321
2255299214cyclictest0-21swapper/112:15:181
22552992119cyclictest0-21swapper/112:35:011
22552992119cyclictest0-21swapper/111:40:191
22552992119cyclictest0-21swapper/110:55:191
22552992119cyclictest0-21swapper/110:35:161
22552992118cyclictest0-21swapper/112:20:161
22552992118cyclictest0-21swapper/109:35:111
2255499204cyclictest0-21swapper/309:45:193
22554992019cyclictest0-21swapper/312:10:163
22554992019cyclictest0-21swapper/312:10:153
22554992018cyclictest0-21swapper/308:50:133
22554992018cyclictest0-21swapper/308:40:163
22553992018cyclictest0-21swapper/209:15:122
2255299204cyclictest0-21swapper/111:25:201
22552992018cyclictest10703-21munin-run12:40:001
22552992018cyclictest0-21swapper/111:20:171
22552992018cyclictest0-21swapper/110:20:161
22552992018cyclictest0-21swapper/107:25:101
22551992018cyclictest0-21swapper/008:10:260
22554991918cyclictest0-21swapper/310:45:163
22554991917cyclictest12044-21dump-pmu-power10:20:003
22554991917cyclictest0-21swapper/308:25:163
22554991917cyclictest0-21swapper/307:10:193
22553991916cyclictest0-21swapper/210:00:172
2255299195cyclictest0-21swapper/110:10:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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