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2025-07-11 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackaslot0.osadl.org (updated Fri Jul 11, 2025 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223112940,1sleep222308-21sshd09:21:002
130832600,0sleep00-21swapper/011:12:260
122762590,6sleep00-21swapper/010:53:150
76832580,1sleep00-21swapper/011:23:470
231412570,1sleep023137-21apache_accesses11:55:120
112272560,1sleep011197-21sshd11:04:490
44902540,1sleep34491-21sshd11:52:513
307872530,1sleep10-21swapper/109:18:181
73952520,0sleep30-21swapper/308:20:213
110562520,0sleep311058-21sshd09:46:283
94572510,0sleep00-21swapper/009:42:250
199532510,0sleep10-21swapper/111:58:381
167732510,0sleep10-21swapper/109:20:231
230092500,0sleep30-21swapper/312:02:533
114062500,0sleep30-21swapper/310:18:053
456724924,8sleep30-21swapper/307:07:253
455124923,8sleep10-21swapper/107:07:141
240572490,0sleep00-21swapper/012:37:310
164982490,1sleep20-21swapper/212:26:312
85642480,0sleep18547-21sshd10:17:431
470424825,19sleep20-21swapper/207:09:032
42922480,2sleep0504499cyclictest11:41:580
86432470,0sleep30-21swapper/309:19:333
449524724,19sleep00-21swapper/007:06:300
45382460,0sleep00-21swapper/011:49:190
325602450,1sleep330090-21diskmemload11:26:363
78592440,0sleep10-21swapper/110:41:341
284322420,0sleep230090-21diskmemload10:16:172
228782410,0sleep339-21ksoftirqd/311:13:383
272942370,2sleep3504799cyclictest11:18:023
189022340,0sleep00-21swapper/009:47:380
504699272,25cyclictest0-21swapper/211:47:252
5044992321,1cyclictest30636-21sshd12:28:060
5047992119,1cyclictest0-21swapper/312:32:183
5047992119,1cyclictest0-21swapper/312:32:183
5046992119,1cyclictest0-21swapper/211:37:122
504699200,19cyclictest0-21swapper/211:06:172
5047991918,1cyclictest0-21swapper/310:55:033
5047991917,1cyclictest0-21swapper/309:37:293
5046991918,1cyclictest27079-21sshd09:36:572
5045991918,1cyclictest24450-21sshd10:39:561
5044991917,1cyclictest31500-21sshd10:12:510
6652180,0sleep01507-21nfsd12:21:290
5046991816,1cyclictest0-21swapper/209:29:002
5044991816,1cyclictest3007-21sshd10:21:010
227192180,0sleep00-21swapper/007:45:140
5046991716,1cyclictest0-21swapper/210:01:002
5045991715,1cyclictest15792-21sshd10:50:021
504499170,6cyclictest0-21swapper/012:19:150
8102160,0sleep30-21swapper/310:25:103
504799165,10cyclictest28605-21sshd11:06:443
5046991615,1cyclictest0-21swapper/209:48:252
5045991614,1cyclictest25796-21sshd10:00:071
5044991615,1cyclictest27215-21sshd10:08:020
504499160,11cyclictest25331-21sshd12:13:520
504499160,10cyclictest6074-21sshd12:04:480
235872160,1sleep30-21swapper/312:16:583
114082160,0sleep111390-21sshd11:08:381
504799159,5cyclictest9852-21sshd10:45:293
504799155,1cyclictest7748-21sshd11:31:133
5047991513,1cyclictest0-21swapper/312:28:453
504799150,4cyclictest0-21swapper/309:57:553
5046991513,1cyclictest0-21swapper/210:22:112
504599152,2cyclictest4542-21sshd09:34:101
504499159,2cyclictest0-21swapper/011:53:490
504499157,3cyclictest0-21swapper/011:35:060
5044991513,1cyclictest3847-21sshd10:45:000
504499150,9cyclictest19670-21bash11:17:050
504499150,14cyclictest0-21swapper/008:20:130
504499150,12cyclictest16173-21sshd09:24:070
3592150,0sleep30-21swapper/310:36:443
18582150,0sleep28-21rcu_preempt10:33:032
504799148,2cyclictest23502-21bash09:32:233
5047991412,1cyclictest0-21swapper/309:24:413
504799140,9cyclictest0-21swapper/309:13:343
504799140,11cyclictest13872-21sshd11:46:413
504799140,11cyclictest0-21swapper/310:53:313
504699141,12cyclictest0-21swapper/212:33:372
504699141,12cyclictest0-21swapper/212:33:372
5046991411,2cyclictest0-21swapper/207:35:182
5046991411,2cyclictest0-21swapper/207:35:182
504699140,1cyclictest18246-21bash09:51:232
504699140,13cyclictest0-21swapper/212:15:572
504699140,13cyclictest0-21swapper/211:18:052
504599140,5cyclictest0-21swapper/112:33:201
504599140,5cyclictest0-21swapper/112:33:201
504599140,5cyclictest0-21swapper/109:35:131
504599140,13cyclictest27833-21sshd11:29:581
504599140,13cyclictest0-21swapper/109:54:181
504599140,10cyclictest0-21swapper/110:25:011
504499149,4cyclictest19089-21bash11:25:090
504499149,4cyclictest0-21swapper/011:06:220
504499149,4cyclictest0-21swapper/010:45:420
504499148,5cyclictest9832-21sshd10:26:030
504499148,3cyclictest0-21swapper/009:35:260
504499147,6cyclictest0-21swapper/009:31:490
504499147,3cyclictest0-21swapper/010:15:490
504499141,1cyclictest115950irq/25-eth009:56:480
504499140,13cyclictest0-21swapper/010:00:200
504499140,13cyclictest0-21swapper/009:52:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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