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2024-07-27 - 07:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Jul 27, 2024 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
784521330,0sleep27816-21sshd21:55:332
305192980,0sleep20-21swapper/200:36:092
143672920,0sleep30-21swapper/321:15:573
143672920,0sleep30-21swapper/321:15:573
138262920,0sleep00-21swapper/022:09:340
164412890,1sleep016432-21bash22:39:070
261332840,0sleep126130-21cp00:08:591
214782710,2sleep31316299cyclictest23:14:193
197372710,1sleep019728-21sshd23:51:340
288422640,0sleep128833-21sshd22:26:461
1274626226,18sleep10-21swapper/119:08:021
311062610,2sleep00-21swapper/022:50:570
268852610,1sleep00-21swapper/021:41:050
96682600,1sleep39659-21sshd22:17:113
1257026022,18sleep30-21swapper/319:05:483
53672590,1sleep20-21swapper/221:15:152
53672590,1sleep20-21swapper/221:15:142
177692580,0sleep017767-21sshd21:10:530
41892570,1sleep21316199cyclictest22:03:222
266522570,1sleep226629-21sshd22:53:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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