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2025-07-12 - 11:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Sat Jul 12, 2025 00:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80702580,1sleep08068-21sshd23:09:310
205442580,0sleep00-21swapper/021:15:490
261182550,1sleep11507-21nfsd00:22:261
44742540,0sleep14473-21sshd21:17:301
33872540,1sleep08-21rcu_preempt21:37:000
278402540,0sleep337-21rcuc/322:21:543
238202540,0sleep00-21swapper/000:10:560
232612540,0sleep323264-21sshd21:52:053
264812530,0sleep10-21swapper/123:57:311
206182530,1sleep320600-21sshd22:57:273
319042510,0sleep30-21swapper/323:21:393
19172510,0sleep30-21swapper/322:09:363
124312510,0sleep3381ktimersoftd/321:21:333
110062510,0sleep10-21swapper/122:49:561
54112500,0sleep00-21swapper/023:38:420
235002500,0sleep30-21swapper/321:42:203
191342500,0sleep20-21swapper/223:00:342
191342500,0sleep20-21swapper/223:00:342
181192500,1sleep318115-21bash23:46:353
37652490,1sleep23753-21sshd21:24:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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