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2025-04-22 - 21:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Tue Apr 22, 2025 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170742960,0sleep117075-21bash12:26:101
75452910,0sleep00-21swapper/010:47:220
189002860,0sleep00-21swapper/011:23:510
280842620,0sleep10-21swapper/111:34:011
168852580,0sleep30-21swapper/309:31:133
239062570,1sleep20-21swapper/209:35:162
89932560,0sleep20-21swapper/211:49:172
233562560,0sleep30-21swapper/310:18:573
16342550,2sleep12459599cyclictest10:36:371
57082540,1sleep10-21swapper/109:26:471
245282540,1sleep024518-21sshd11:12:180
194032540,1sleep219393-21sshd11:50:092
254532530,0sleep017080-21diskmemload11:58:570
247452530,0sleep10-21swapper/110:55:401
9632510,0sleep30-21swapper/310:53:223
69122510,0sleep10-21swapper/109:54:021
70492500,0sleep17012-21sshd09:30:161
2406125023,9sleep00-21swapper/007:06:320
198622500,0sleep019863-21sshd11:27:040
72662490,0sleep30-21swapper/311:10:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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