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2024-02-29 - 09:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Thu Feb 29, 2024 00:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1117227027,29sleep10-21swapper/119:07:101
7572630,0sleep119-21rcuc/123:11:411
325672630,0sleep20-21swapper/200:03:252
83242620,1sleep21784-21runrttasks23:06:372
259342590,0sleep00-21swapper/000:30:040
1113625924,19sleep20-21swapper/219:06:432
75212580,0sleep30-21swapper/300:20:383
322422570,1sleep032233-21sshd23:03:100
322422570,1sleep032233-21sshd23:03:100
315812570,1sleep131573-21rm22:20:161
227152570,0sleep20-21swapper/221:44:042
210902560,1sleep021083-21sshd21:14:250
128242560,1sleep212822-21sshd21:10:392
47672550,0sleep30-21swapper/300:07:043
312952550,0sleep21546-21nfsd23:34:142
278972550,0sleep10-21swapper/123:02:471
278972550,0sleep10-21swapper/123:02:471
219642550,0sleep10-21swapper/121:26:121
220052540,0sleep30-21swapper/323:33:223
138232540,0sleep313822-21sshd21:16:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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