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2024-02-23 - 07:56
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Note that this system runs a non-optimized debug kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 100 highest latencies:
System rackbslot0.osadl.org (updated Fri Feb 23, 2024 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5186
"cycles":100000000,5185
"load":"idle",5184
"condition":{5183
"clock":"2500"5181
"family":"x86",5180
"vendor":"Intel",5179
"processor":{5177
"dataset":"2024-01-08T15:38:16+0100"5175
"origin":"2024-01-08T12:43:22+0100",5174
"timestamps":{5173
"granularity":"microseconds"5171
6108:13:255169
41,08:13:055168
57,08:13:215167
43,08:13:075166
"maxima":[5165
008:12:245162
0,08:12:245161
0,08:12:245160
0,08:12:245159
0,08:12:245158
0,08:12:245157
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0,08:12:245120
0,08:12:245119
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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