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2024-07-22 - 03:43
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Note that this system runs a non-optimized debug kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Characteristics of the 100 highest latencies:
System rackbslot0.osadl.org (updated Mon Jul 22, 2024 00:45:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5186
"cycles":100000000,5185
"load":"idle",5184
"condition":{5183
"clock":"2500"5181
"family":"x86",5180
"vendor":"Intel",5179
"processor":{5177
"dataset":"2024-01-08T15:38:16+0100"5175
"origin":"2024-01-08T12:43:22+0100",5174
"timestamps":{5173
"granularity":"microseconds"5171
6117:39:155169
41,17:38:555168
57,17:39:115167
43,17:38:575166
"maxima":[5165
017:38:145162
0,17:38:145161
0,17:38:145160
0,17:38:145159
0,17:38:145158
0,17:38:145157
0,17:38:145156
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0,17:38:145124
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0,17:38:145121
0,17:38:145120
0,17:38:145119
0,17:38:145118
0,17:38:145117
0,17:38:145116
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0,17:38:145112
0,17:38:145111
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0,17:38:145109
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0,17:38:145107
0,17:38:145106
0,17:38:145105
0,17:38:145104
0,17:38:145103
0,17:38:145102
0,17:38:145101
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0,17:38:145099
0,17:38:145098
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0,17:38:145080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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