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2021-09-17 - 21:38

ARMv7 Processor rev 4 (v7l), Linux 4.6.5-rt10-v7 (Profile)

Latency plot of system in rack #b, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the alll highest latencies:
System rackbslot3.osadl.org (updated Fri Jun 11, 2021 15:37:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1234299195127,9cyclictest3-21ksoftirqd/014:43:110
1234399156140,11cyclictest24-21ksoftirqd/114:38:341
123439914953,6cyclictest24-21ksoftirqd/115:15:001
12345991413,7cyclictest0-21swapper/315:05:533
12345991413,7cyclictest0-21swapper/315:05:533
1234399139129,6cyclictest24-21ksoftirqd/114:44:291
1234399137104,12cyclictest24-21ksoftirqd/115:05:271
1234399137104,12cyclictest24-21ksoftirqd/115:05:271
1234299133106,10cyclictest3-21ksoftirqd/015:06:460
1234299133106,10cyclictest3-21ksoftirqd/015:06:460
123439912492,8cyclictest24-21ksoftirqd/115:35:011
1234599123112,5cyclictest42-21ksoftirqd/314:44:283
1234299122113,5cyclictest3-21ksoftirqd/015:11:190
123439912196,9cyclictest24-21ksoftirqd/115:05:001
1234299119109,6cyclictest3-21ksoftirqd/014:37:380
123449911699,12cyclictest33-21ksoftirqd/215:07:132
123449911699,12cyclictest33-21ksoftirqd/215:07:132
1234299111101,6cyclictest3-21ksoftirqd/015:16:540
1234399109101,4cyclictest231ktimersoftd/115:15:451
123439910898,6cyclictest24-21ksoftirqd/115:25:011
123429910781,9cyclictest3-21ksoftirqd/014:30:550
123439910675,8cyclictest24-21ksoftirqd/114:50:011
123429910677,7cyclictest3-21ksoftirqd/014:46:060
123459910594,7cyclictest42-21ksoftirqd/315:15:453
123429910590,9cyclictest3-21ksoftirqd/015:05:010
123429910495,6cyclictest3-21ksoftirqd/015:20:080
123429910474,10cyclictest3-21ksoftirqd/015:29:030
123459910264,33cyclictest42-21ksoftirqd/315:21:173
123439910170,8cyclictest24-21ksoftirqd/115:00:011
123429910081,7cyclictest3-21ksoftirqd/015:35:010
12344999986,10cyclictest33-21ksoftirqd/214:44:302
1234399992,8cyclictest81rcu_preempt15:29:031
12345999867,26cyclictest42-21ksoftirqd/315:14:473
12345999764,29cyclictest42-21ksoftirqd/314:46:253
12345999660,31cyclictest42-21ksoftirqd/315:26:293
12344999687,5cyclictest0-21swapper/215:16:592
12344999665,27cyclictest33-21ksoftirqd/215:12:392
12345999465,25cyclictest42-21ksoftirqd/314:56:453
1234399942,5cyclictest81rcu_preempt14:30:581
12342999467,9cyclictest3-21ksoftirqd/014:55:030
12342999365,7cyclictest3-21ksoftirqd/014:52:090
12345999263,25cyclictest42-21ksoftirqd/314:33:313
12345999181,6cyclictest42-21ksoftirqd/314:52:013
12345999167,20cyclictest42-21ksoftirqd/315:04:483
12345999164,23cyclictest42-21ksoftirqd/315:31:373
12344999162,25cyclictest33-21ksoftirqd/214:31:442
12344999053,32cyclictest33-21ksoftirqd/214:59:482
12343998959,8cyclictest24-21ksoftirqd/114:50:311
12344998854,29cyclictest33-21ksoftirqd/215:03:522
12344998661,21cyclictest33-21ksoftirqd/214:45:282
12345998473,6cyclictest42-21ksoftirqd/314:36:093
12344998153,23cyclictest33-21ksoftirqd/214:52:372
12344998131,23cyclictest33-21ksoftirqd/214:36:132
12344998051,25cyclictest33-21ksoftirqd/215:30:232
12344997161,6cyclictest33-21ksoftirqd/215:25:102
12344997061,6cyclictest33-21ksoftirqd/215:24:042
119799540,8rtkit-daemon1196-21rtkit-daemon14:28:110
117282477,9sleep20-21swapper/214:25:192
118032467,9sleep10-21swapper/114:26:181
117692358,19sleep30-21swapper/314:25:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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