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2023-02-02 - 15:54

x86 VIA QuadCore L4700 @1200 MHz, Linux 3.18.43-rt46 (Profile)

Latency plot of system in rack #b, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rackbslot4.osadl.org (updated Thu Feb 02, 2023 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5735996628,7cyclictest15419-21sadc09:48:350
5735995912,19cyclictest0-21swapper/010:26:560
573599583,49cyclictest0-21swapper/012:04:280
575399574,47cyclictest0-21swapper/309:49:153
573599574,48cyclictest0-21swapper/011:52:420
573599564,47cyclictest0-21swapper/009:55:160
75502550,7sleep20-21swapper/211:50:472
573599554,45cyclictest32458-21ssh10:11:220
573599554,45cyclictest0-21swapper/011:55:300
573599554,45cyclictest0-21swapper/011:55:300
575399544,26cyclictest0-21swapper/309:35:033
573599545,44cyclictest0-21swapper/009:22:540
575399534,43cyclictest0-21swapper/309:46:533
5753995316,32cyclictest657-21runrttasks08:20:443
575399528,39cyclictest0-21swapper/311:56:523
575399528,39cyclictest0-21swapper/311:56:523
575399527,5cyclictest0-21swapper/312:21:203
5753995242,5cyclictest37-21ksoftirqd/310:08:353
575399524,44cyclictest0-21swapper/310:57:583
575399524,42cyclictest0-21swapper/311:18:413
5753995224,5cyclictest37-21ksoftirqd/309:08:373
573599525,41cyclictest0-21swapper/010:59:020
573599523,44cyclictest0-21swapper/010:51:110
575399517,38cyclictest0-21swapper/309:16:303
575399517,38cyclictest0-21swapper/309:16:303
575399517,19cyclictest0-21swapper/312:15:383
575399516,39cyclictest0-21swapper/311:49:533
575399515,40cyclictest0-21swapper/307:09:133
575399514,42cyclictest0-21swapper/312:09:453
575399514,42cyclictest0-21swapper/309:21:453
575399514,41cyclictest0-21swapper/311:06:013
575399514,41cyclictest0-21swapper/311:06:013
575399514,22cyclictest0-21swapper/311:45:373
575399512,43cyclictest24851-21ssh11:29:223
573599519,37cyclictest0-21swapper/011:22:510
573599513,7cyclictest0-21swapper/010:44:470
573599513,44cyclictest0-21swapper/011:24:520
573599513,25cyclictest0-21swapper/010:33:350
5735995110,14cyclictest0-21swapper/012:12:390
573599511,4cyclictest6374-21ls12:33:530
575399508,37cyclictest0-21swapper/311:41:103
575399507,38cyclictest0-21swapper/312:31:253
575399506,38cyclictest0-21swapper/310:48:013
575399504,41cyclictest0-21swapper/311:59:003
575399504,41cyclictest0-21swapper/310:52:163
575399504,41cyclictest0-21swapper/310:11:323
575399504,41cyclictest0-21swapper/309:25:053
575399504,41cyclictest0-21swapper/308:09:033
575399504,40cyclictest0-21swapper/310:42:123
575399504,21cyclictest0-21swapper/312:26:183
5753995012,6cyclictest0-21swapper/310:22:103
573599503,42cyclictest0-21swapper/012:26:290
573599503,42cyclictest0-21swapper/011:40:580
573599503,41cyclictest586-21irqbalance09:26:430
575399496,39cyclictest0-21swapper/310:01:503
575399496,38cyclictest0-21swapper/312:07:203
575399496,38cyclictest0-21swapper/311:11:443
575399496,38cyclictest0-21swapper/310:32:093
575399496,38cyclictest0-21swapper/310:27:313
575399495,38cyclictest0-21swapper/307:59:063
575399494,40cyclictest0-21swapper/312:37:493
575399494,40cyclictest0-21swapper/311:14:263
575399494,40cyclictest0-21swapper/309:08:403
575399494,39cyclictest0-21swapper/309:43:113
575399494,39cyclictest0-21swapper/307:48:583
575399494,17cyclictest0-21swapper/311:25:423
575399492,42cyclictest37-21ksoftirqd/310:37:323
575399492,41cyclictest2325-21runrttasks10:14:123
575399492,41cyclictest2325-21runrttasks10:14:123
573599495,38cyclictest0-21swapper/011:16:490
573599495,38cyclictest0-21swapper/010:39:570
573599495,16cyclictest0-21swapper/009:17:570
573599495,16cyclictest0-21swapper/009:17:570
573599494,9cyclictest0-21swapper/012:18:100
573599494,40cyclictest0-21swapper/009:10:330
573599493,42cyclictest0-21swapper/010:53:510
573599493,40cyclictest0-21swapper/009:59:370
575399485,38cyclictest0-21swapper/308:39:013
575399484,39cyclictest0-21swapper/310:58:513
575399484,38cyclictest0-21swapper/309:29:063
575399484,19cyclictest0-21swapper/308:04:163
575399484,18cyclictest0-21swapper/309:53:463
574599481,42cyclictest6238-21uptime09:34:132
573599484,40cyclictest0-21swapper/011:03:450
573599484,40cyclictest0-21swapper/011:03:450
573599484,40cyclictest0-21swapper/010:37:020
573599484,38cyclictest0-21swapper/009:40:030
573599484,19cyclictest0-21swapper/009:32:580
573599483,7cyclictest0-21swapper/011:13:010
573599483,41cyclictest0-21swapper/012:31:190
5735994812,8cyclictest0-21swapper/009:51:370
575399474,39cyclictest0-21swapper/307:29:173
575399474,38cyclictest0-21swapper/308:43:583
575399474,38cyclictest0-21swapper/307:14:203
575399473,40cyclictest0-21swapper/311:34:033
575399473,40cyclictest0-21swapper/308:33:063
575399473,40cyclictest0-21swapper/307:43:593
5753994714,7cyclictest683-21sshd07:56:203
573599477,35cyclictest0-21swapper/010:17:550
573599477,35cyclictest0-21swapper/010:17:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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