You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-02-06 - 23:04

x86 VIA QuadCore L4700 @1200 MHz, Linux 3.18.43-rt46 (Profile)

Latency plot of system in rack #b, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot4.osadl.org (updated Mon Feb 06, 2023 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2090399754,48cyclictest0-21swapper/011:37:410
2057226613,18sleep00-21swapper/007:05:300
2061026013,17sleep20-21swapper/207:05:562
2090799574,47cyclictest0-21swapper/111:41:121
2090799573,49cyclictest0-21swapper/110:49:231
2090799564,26cyclictest0-21swapper/110:37:271
2090799563,47cyclictest19101-21ssh11:08:031
2090799563,47cyclictest19101-21ssh11:08:031
2091899544,6cyclictest0-21swapper/307:28:283
2091899542,8cyclictest29397-21/usr/sbin/munin10:37:033
2091299542,46cyclictest3997-21sh09:08:542
2090799546,43cyclictest0-21swapper/111:45:441
2090799543,46cyclictest0-21swapper/107:50:571
2091899535,42cyclictest0-21swapper/308:48:463
2091899534,42cyclictest0-21swapper/308:42:463
20918995317,31cyclictest2195-21sh10:00:543
2091299535,41cyclictest0-21swapper/211:15:072
2090399534,43cyclictest0-21swapper/012:27:260
2091899525,41cyclictest0-21swapper/310:47:333
2091899524,41cyclictest0-21swapper/312:36:213
2091299524,41cyclictest0-21swapper/209:48:042
2090799524,42cyclictest0-21swapper/108:57:261
2090799523,8cyclictest0-21swapper/108:03:141
2090799523,44cyclictest0-21swapper/110:30:411
2090799523,44cyclictest0-21swapper/108:34:161
2090799523,42cyclictest0-21swapper/111:04:331
2090799523,42cyclictest0-21swapper/111:04:331
2090799522,44cyclictest16254-21ssh10:20:051
2090399525,41cyclictest0-21swapper/011:55:520
2090399523,43cyclictest0-21swapper/011:36:250
2090399522,6cyclictest31386-21latency_hist12:11:240
20903995212,35cyclictest6163-21latency_hist12:21:240
2091899514,41cyclictest0-21swapper/310:16:343
2091899514,40cyclictest0-21swapper/308:53:163
2091299514,42cyclictest0-21swapper/209:45:442
2091299514,22cyclictest0-21swapper/211:35:512
2091299514,22cyclictest0-21swapper/210:36:492
2091299514,14cyclictest0-21swapper/208:42:032
2090799514,41cyclictest0-21swapper/112:14:341
2090799514,41cyclictest0-21swapper/111:11:571
2090799513,43cyclictest0-21swapper/108:14:411
2090799513,25cyclictest0-21swapper/112:10:201
2090399514,41cyclictest0-21swapper/009:03:350
2091899504,41cyclictest0-21swapper/311:31:543
2091899504,40cyclictest0-21swapper/310:52:263
2091899504,40cyclictest0-21swapper/308:56:583
2091899504,40cyclictest0-21swapper/308:22:073
2091899504,40cyclictest0-21swapper/308:22:073
2091899504,40cyclictest0-21swapper/308:13:373
2091899503,7cyclictest7907-21ssh11:37:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional