You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-19 - 09:35

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #b, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Phytec
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot5s.osadl.org (updated Fri Apr 19, 2024 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2536828998274,5cyclictest2609879-21kworker/u8:2+events_unbound23:02:441
2536828996759,6cyclictest2599561-21kworker/u8:2+events_unbound22:07:331
2536828996356,5cyclictest2640911-21kworker/u8:3+events_unbound00:12:571
2536828996356,5cyclictest2640911-21kworker/u8:3+events_unbound00:12:571
2536828995851,5cyclictest2532929-21kworker/u8:0+events_unbound19:20:211
2536828995851,5cyclictest2532929-21kworker/u8:0+events_unbound19:20:201
2536841995649,4cyclictest2625607-21kworker/u8:3+events_unbound23:50:173
2536828995650,4cyclictest2558517-21kworker/u8:1+events_unbound21:17:251
2536828995650,4cyclictest2558517-21kworker/u8:1+events_unbound21:17:251
2536828995448,4cyclictest2544073-21kworker/u8:3+events_unbound19:37:131
2536828995447,5cyclictest2532929-21kworker/u8:0+events_unbound19:10:191
2536828995445,5cyclictest2596218-21kworker/u8:0+events_unbound00:20:161
2536828995445,5cyclictest2596218-21kworker/u8:0+events_unbound00:20:161
2536834994626,16cyclictest0-21swapper/222:00:002
2536828994639,4cyclictest2549170-21kworker/u8:0+events_unbound19:42:151
2536828994639,4cyclictest2549170-21kworker/u8:0+events_unbound19:42:151
2536828994538,5cyclictest2618296-21kworker/u8:1+events_unbound23:17:461
2536841994432,9cyclictest391ktimers/322:05:133
2536828994437,5cyclictest2640911-21kworker/u8:3+events_unbound00:30:271
2536828994437,5cyclictest2558517-21kworker/u8:1+events_unbound20:25:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional