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2022-01-22 - 15:15

Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz, Linux 2.6.33.7.2-rt30-32 (Profile)

Latency plot of system in rack #b, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot5.osadl.org (updated Sat Jan 22, 2022 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
939023534sleep20-21swapper19:39:122
346723130sleep20-21swapper21:26:362
392923029sleep20-21swapper19:27:592
339523029sleep20-21swapper20:26:342
339523029sleep20-21swapper20:26:342
3069623029sleep20-21swapper21:19:402
3065823029sleep20-21swapper20:16:412
2576023029sleep20-21swapper18:08:122
2303323029sleep20-21swapper18:02:362
2255923029sleep20-21swapper21:03:232
2232723029sleep20-21swapper20:01:292
1717623029sleep20-21swapper18:51:342
1684523025sleep20-21swapper19:51:282
1458323029sleep20-21swapper20:49:142
133523029sleep20-21swapper19:25:112
7235992911cyclictest0-21swapper18:10:470
7235992827cyclictest21550irq/16-uhci_hcd19:15:360
7235992812cyclictest0-21swapper18:57:250
7235992726cyclictest21550irq/16-uhci_hcd20:02:200
7235992726cyclictest21550irq/16-uhci_hcd17:45:280
7235992725cyclictest21550irq/16-uhci_hcd19:47:160
7235992725cyclictest21550irq/16-uhci_hcd19:37:190
7235992725cyclictest21550irq/16-uhci_hcd18:48:220
7235992715cyclictest813349md0_resync20:24:590
7235992712cyclictest0-21swapper22:33:350
7235992712cyclictest0-21swapper22:24:080
7235992712cyclictest0-21swapper21:55:520
7235992712cyclictest0-21swapper19:51:150
7235992712cyclictest0-21swapper19:09:480
7235992712cyclictest0-21swapper17:55:190
7235992711cyclictest0-21swapper22:38:220
7235992711cyclictest0-21swapper22:26:240
7235992711cyclictest0-21swapper22:09:290
7235992711cyclictest0-21swapper21:43:110
7235992711cyclictest0-21swapper20:44:310
7235992711cyclictest0-21swapper20:18:320
7235992711cyclictest0-21swapper20:13:360
7235992711cyclictest0-21swapper20:07:140
7235992711cyclictest0-21swapper19:58:170
7235992711cyclictest0-21swapper19:44:380
7235992711cyclictest0-21swapper19:33:160
7235992711cyclictest0-21swapper19:22:240
7235992711cyclictest0-21swapper19:16:460
7235992711cyclictest0-21swapper18:20:370
7235992711cyclictest0-21swapper17:56:290
667622727sleep20-21swapper19:33:522
3124422723sleep20-21swapper18:19:572
3106122727sleep20-21swapper19:19:512
2231922727sleep20-21swapper23:05:042
2231922727sleep20-21swapper23:05:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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