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2026-02-11 - 04:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Wed Feb 11, 2026 00:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22883223414,113sleep122913-21fschecks_time19:03:311
240789912158,8cyclictest5469-21ssh21:17:530
2389721186,18sleep00-21swapper/019:06:400
24078991174,41cyclictest13743-21/usr/sbin/munin21:32:580
24078991174,41cyclictest13743-21/usr/sbin/munin21:32:580
24078991173,44cyclictest26719-21proc_pri20:52:520
24078991163,85cyclictest14383-21apt-get22:27:470
240789911637,12cyclictest12072-21apt-get00:12:350
240789911418,65cyclictest3062-21apt-get23:02:510
2409399983,78cyclictest12645-21chrt00:12:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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