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2025-04-22 - 21:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot7.osadl.org (updated Tue Apr 22, 2025 12:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22383213243,57sleep222398-21cpu07:04:592
23825991313,101cyclictest3225-21sshd09:15:120
238259912140,9cyclictest0-21swapper/010:24:380
238259911632,13cyclictest15450irq/292-2188000.ethernet11:19:400
238259911513,41cyclictest316-21in:imuxsock09:29:380
238259911513,41cyclictest316-21in:imuxsock09:29:380
238389911388,11cyclictest181rcu_preempt09:24:533
238389911388,11cyclictest181rcu_preempt09:24:533
238259911341,10cyclictest0-21swapper/007:34:380
23825991133,40cyclictest16479-21mandb08:20:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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