You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-05-25 - 21:21

ARM Xilinx Zync @666 MHz, Linux 3.12.24-rt38 (Profile)

Latency plot of system in rack #b, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackbslot8.osadl.org (updated Fri May 20, 2022 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20199900ksoftirqd/10-21swapper/119:09:041
15369999320cyclictest0-21swapper/019:56:540
15369999118cyclictest0-21swapper/021:05:140
15369999118cyclictest0-21swapper/021:05:140
15369999118cyclictest0-21swapper/000:19:540
15369999017cyclictest0-21swapper/023:35:210
15369999017cyclictest0-21swapper/021:45:280
15369999017cyclictest0-21swapper/020:25:160
15369998916cyclictest0-21swapper/021:10:020
15369998815cyclictest0-21swapper/023:00:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional