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2026-02-12 - 08:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Thu Feb 12, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587503055130irq/54-eth00-21swapper/119:05:491
13542998512cyclictest30405-21aten_rbpower_vo20:00:071
1354299774cyclictest0-21swapper/120:54:521
13541997236cyclictest26114-21munin-node0
13541997236cyclictest16176-21cat20:55:130
13541997236cyclictest10714-21munin-run20:39:520
13541997135cyclictest312272chrt20:01:170
13541997135cyclictest25348-21latency_hist19:44:530
13541997135cyclictest24297-21munin-node0
13541997135cyclictest16844-21sshd00:18:290
13541997034cyclictest8069-21ntp_states23:50:140
13541997034cyclictest6700-21munin-node0
13541997034cyclictest5083-21munin-node0
13541997034cyclictest0-21swapper/019:35:060
13541996933cyclictest0-21swapper/021:40:300
13541996933cyclictest0-21swapper/000:27:160
13541996832cyclictest0-21swapper/000:14:350
13541996749cyclictest29107-21awk23:15:130
13541996731cyclictest19180-21df19:25:090
1354299638cyclictest0-21swapper/122:30:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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