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2022-12-02 - 21:00

ARM Xilinx Zync @666 MHz, Linux 3.12.24-rt38 (Profile)

Latency plot of system in rack #b, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Fri Dec 02, 2022 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587504738530irq/54-eth00-21swapper/107:07:571
151100080rcuc/00-21swapper/007:06:300
502998310cyclictest783-21df07:10:220
50299829cyclictest9317-21munin-node0
50299796cyclictest1429-21munin-node0
50299785cyclictest28731-21modprobe08:35:180
50299785cyclictest0-21swapper/011:35:060
50299774cyclictest8423-21latency12:30:290
50299774cyclictest4343-21munin-node0
50299774cyclictest11599-21missed_timers11:00:330
50299774cyclictest0-21swapper/010:00:400
50299774cyclictest0-21swapper/009:00:230
50299774cyclictest0-21swapper/008:50:340
50299774cyclictest0-21swapper/008:40:170
50299763cyclictest9851-21ps07:35:340
50299763cyclictest9851-21ps07:35:340
50299763cyclictest18837-21idleruntime-cro08:05:050
50299763cyclictest17339-21idleruntime-cro09:40:050
502997621cyclictest27384-21fschecks_count08:30:280
503997520cyclictest1208-21wc10:30:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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