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2023-03-28 - 23:38

ARM Xilinx Zync @666 MHz, Linux 3.12.24-rt38 (Profile)

Latency plot of system in rack #b, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Tue Mar 28, 2023 12:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
587501764510irq/54-eth00-21swapper/107:09:541
3197690ksoftirqd/00-21swapper/007:07:250
28321999017cyclictest8716-21sensors09:25:370
28321999017cyclictest10210-21munin-node0
28321998916cyclictest0-21swapper/007:20:350
28321998613cyclictest20719-21latency_hist08:24:590
28321998613cyclictest0-21swapper/011:03:080
28321998613cyclictest0-21swapper/008:45:110
28321998411cyclictest0-21swapper/009:40:200
28321998411cyclictest0-21swapper/008:09:070
28321998411cyclictest0-21swapper/007:56:380
28321998411cyclictest0-21swapper/007:56:380
28321998310cyclictest7813-21munin-node0
28321998310cyclictest21026-21wc08:25:150
28321998310cyclictest0-21swapper/012:35:210
28321998310cyclictest0-21swapper/011:45:210
2832199829cyclictest3246-21cpu09:10:150
2832199829cyclictest22415-21modprobe10:09:290
2832199829cyclictest18443-21missed_timers11:35:230
28321998227cyclictest0-21swapper/012:00:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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