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2019-07-17 - 02:53

ARMv7 Processor rev 0 (v7l), Linux 3.12.24-rt38 (Profile)

Latency plot of system in rack #b, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
The worst-case latency is NOT higher under extreme CPU load.
Results of all systems under extreme CPU load are combined on this summary graph.
Characteristics of the 20 highest latencies:
System rackbslot8.osadl.org (updated Wed Jul 17, 2019 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
675299964cyclictest0-21swapper/023:57:410
6752999219cyclictest0-21swapper/020:20:190
6752999219cyclictest0-21swapper/000:00:120
6752999118cyclictest3799-21aten_rbpower_vo23:45:060
6752999118cyclictest11528-21grep19:25:020
6752999118cyclictest0-21swapper/022:30:130
6752999118cyclictest0-21swapper/000:35:100
6752999017cyclictest0-21swapper/020:49:310
6752999017cyclictest0-21swapper/020:35:220
6752999017cyclictest0-21swapper/020:15:060
6752998916cyclictest0-21swapper/023:25:070
6752998916cyclictest0-21swapper/023:04:030
6752998916cyclictest0-21swapper/022:07:460
6752998916cyclictest0-21swapper/022:00:530
6752998916cyclictest0-21swapper/021:21:140
6752998815cyclictest0-21swapper/023:54:140
6752998815cyclictest0-21swapper/023:54:140
6752998815cyclictest0-21swapper/022:25:200
6752998815cyclictest0-21swapper/020:55:320
6752998815cyclictest0-21swapper/020:52:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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