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2025-04-18 - 16:07

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Fri Apr 18, 2025 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37925692131117,9sleep30-21swapper/307:05:013
37950342130101,9sleep00-21swapper/007:09:220
37949342126111,10sleep20-21swapper/207:07:572
37948452124110,9sleep50-21swapper/507:06:405
37950262123108,10sleep10-21swapper/107:09:161
37949632123109,9sleep40-21swapper/407:08:234
37947732119105,9sleep70-21swapper/707:05:377
37929712117103,9sleep60-21swapper/607:05:126
379532599103100,3cyclictest573-21snmpd08:06:105
3795312991031,3cyclictest31-21ksoftirqd/211:43:552
37953259910299,3cyclictest573-21snmpd08:35:225
3795303991020,99cyclictest0-21swapper/007:32:180
3795331991010,100cyclictest0-21swapper/711:33:537
3795331991010,100cyclictest0-21swapper/711:19:587
37953279910199,2cyclictest3890256-21kworker/6:011:44:386
37953279910199,2cyclictest3890256-21kworker/6:010:45:276
37953279910199,2cyclictest3890256-21kworker/6:010:45:276
37953279910199,1cyclictest3844409-21kworker/6:109:37:196
379532799101100,1cyclictest4037369-21kworker/6:112:36:386
379532799101100,1cyclictest4037369-21kworker/6:112:32:316
379532799101100,1cyclictest3890256-21kworker/6:011:30:576
379532799101100,1cyclictest3890256-21kworker/6:011:25:016
379532799101100,1cyclictest3890256-21kworker/6:011:23:456
379532799101100,1cyclictest3890256-21kworker/6:011:08:116
379532799101100,1cyclictest3890256-21kworker/6:010:50:006
379532799101100,1cyclictest3890256-21kworker/6:010:10:346
379532799101100,1cyclictest3890256-21kworker/6:009:56:096
379532799101100,1cyclictest3844409-21kworker/6:109:30:596
379532799101100,1cyclictest3844409-21kworker/6:109:27:026
379532799101100,1cyclictest3374551-21kworker/6:207:15:136
37953259910199,2cyclictest573-21snmpd11:57:125
37953259910199,1cyclictest603-21lldpd10:34:385
37953259910199,1cyclictest573-21snmpd07:53:575
37953259910198,3cyclictest573-21snmpd09:53:285
37953259910198,3cyclictest573-21snmpd08:03:435
3795325991010,101cyclictest0-21swapper/510:09:405
3795325991010,100cyclictest0-21swapper/508:50:185
3795325991010,100cyclictest0-21swapper/507:44:155
37953209910199,2cyclictest573-21snmpd11:16:014
37953209910199,1cyclictest573-21snmpd08:11:214
37953129910199,2cyclictest573-21snmpd11:17:372
379531299101100,1cyclictest573-21snmpd12:09:392
37953089910199,2cyclictest573-21snmpd09:41:311
3795308991010,100cyclictest0-21swapper/108:05:341
37953039910196,2cyclictest573-21snmpd11:37:230
379530399101100,1cyclictest573-21snmpd09:40:580
3795303991010,100cyclictest0-21swapper/010:55:150
3795303991010,0cyclictest0-21swapper/011:06:510
3795331991000,99cyclictest0-21swapper/712:04:037
3795331991000,99cyclictest0-21swapper/711:45:167
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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