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2024-04-20 - 00:19

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Fri Apr 19, 2024 12:44:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30339732130118,8sleep00-21swapper/007:05:550
30321462126113,8sleep10-21swapper/107:05:081
30340502125111,9sleep30-21swapper/307:07:023
30340972122108,9sleep50-21swapper/507:07:435
30341282120105,10sleep70-21swapper/707:08:097
30341702119105,9sleep40-21swapper/407:08:464
30340152119105,9sleep60-21swapper/607:06:326
30340382117102,10sleep20-21swapper/207:06:532
303449799102100,2cyclictest721930-21snmpd09:36:251
3034520991010,100cyclictest0-21swapper/708:30:327
30345099910199,2cyclictest721930-21snmpd12:23:224
3034500991010,100cyclictest0-21swapper/212:31:252
3034497991010,101cyclictest0-21swapper/111:04:081
30344929910199,2cyclictest721930-21snmpd10:16:290
303449299101100,1cyclictest721930-21snmpd10:51:100
3034520991000,99cyclictest0-21swapper/709:51:377
3034520991000,100cyclictest0-21swapper/712:13:077
3034520991000,100cyclictest0-21swapper/711:33:417
3034520991000,100cyclictest0-21swapper/711:01:247
3034520991000,100cyclictest0-21swapper/709:47:017
30345169910099,1cyclictest721930-21snmpd11:40:216
30345169910099,1cyclictest721930-21snmpd11:20:466
30345169910099,1cyclictest721930-21snmpd11:05:056
30345169910099,1cyclictest721930-21snmpd10:42:526
30345169910099,1cyclictest721930-21snmpd09:48:316
30345169910099,1cyclictest721930-21snmpd09:35:066
30345169910099,1cyclictest721930-21snmpd08:55:516
30345169910099,1cyclictest721930-21snmpd08:53:506
30345169910099,1cyclictest721930-21snmpd08:40:346
30345169910099,1cyclictest2443439-21ntpd11:03:416
30345169910099,1cyclictest0-21swapper/612:28:326
30345169910098,1cyclictest721930-21snmpd08:11:286
3034516991000,100cyclictest0-21swapper/611:29:196
30345149910099,1cyclictest721930-21snmpd11:37:485
30345149910099,1cyclictest721930-21snmpd10:36:535
30345149910099,1cyclictest721930-21snmpd09:28:195
30345149910098,2cyclictest721930-21snmpd11:03:225
3034514991000,99cyclictest0-21swapper/511:48:265
3034514991000,99cyclictest0-21swapper/511:15:345
3034514991000,99cyclictest0-21swapper/507:25:535
3034514991000,100cyclictest0-21swapper/512:19:215
3034514991000,100cyclictest0-21swapper/508:06:105
3034514991000,100cyclictest0-21swapper/508:00:465
30345099910099,1cyclictest721930-21snmpd11:16:254
30345099910099,1cyclictest721930-21snmpd11:08:564
30345099910099,1cyclictest721930-21snmpd09:58:404
30345099910099,1cyclictest721930-21snmpd07:41:304
30345099910098,1cyclictest721930-21snmpd09:05:454
3034509991000,99cyclictest0-21swapper/410:15:124
3034509991000,99cyclictest0-21swapper/410:10:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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