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2024-04-13 - 04:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot1.osadl.org (updated Sat Apr 13, 2024 01:41:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3200:40:449084
16,00:40:139083
36,00:40:139082
32,00:40:139081
33,00:40:139080
33,00:40:139079
30,00:40:139078
17,00:40:139077
34,00:40:139076
36,00:40:139075
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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