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2023-10-05 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot1.osadl.org (updated Thu Oct 05, 2023 00:48:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
699929185,4sleep50-21swapper/519:07:527
708028172,6sleep60-21swapper/619:09:058
703127367,4sleep110-21swapper/1119:08:223
686627164,5sleep30-21swapper/319:06:015
685126660,4sleep10-21swapper/119:05:481
481726660,4sleep80-21swapper/819:05:1910
714426558,5sleep20-21swapper/219:10:024
46802650,0sleep10-21swapper/100:30:021
698526253,6sleep40-21swapper/419:07:396
714226055,4sleep00-21swapper/019:10:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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