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2021-06-17 - 19:47

Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot1.osadl.org (updated Thu Jun 10, 2021 12:48:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
395499990,89rtkit-daemon0-21swapper/007:07:260
2740528071,6sleep110-21swapper/1107:08:133
2725527664,8sleep10-21swapper/107:06:031
2739727161,7sleep50-21swapper/507:08:087
2733927060,6sleep40-21swapper/407:07:186
2738726959,7sleep80-21swapper/807:07:5810
2726426858,7sleep100-21swapper/1007:06:112
2750826758,6sleep20-21swapper/207:09:414
2751326646,6sleep70-21swapper/707:09:469
2725026655,7sleep90-21swapper/907:05:5811
2723026455,6sleep30-21swapper/307:05:405
2634126152,6sleep60-21swapper/607:05:198
99382550,1sleep110-21swapper/1111:40:573
190572530,1sleep92800899cyclictest11:52:5811
190572530,1sleep92800899cyclictest11:52:5711
13962460,1sleep50-21swapper/511:32:277
97732440,1sleep50-21swapper/510:27:067
188132430,1sleep102801599cyclictest11:52:112
188132430,1sleep102801599cyclictest11:52:102
54352380,1sleep30-21swapper/310:21:405
23442330,0sleep10124-21ksoftirqd/1009:05:152
2795399244,13cyclictest0-21swapper/012:15:010
2795399244,13cyclictest0-21swapper/012:15:000
2796599234,14cyclictest0-21swapper/209:05:004
2795399224,14cyclictest0-21swapper/008:05:010
2798399212,16cyclictest0-21swapper/512:01:497
2798399212,16cyclictest0-21swapper/512:01:487
2795399212,15cyclictest0-21swapper/010:35:000
2801999204,11cyclictest0-21swapper/1110:05:003
2800299203,12cyclictest0-21swapper/808:15:0010
2796599204,12cyclictest0-21swapper/209:15:004
2796599204,11cyclictest0-21swapper/210:30:004
2796599204,10cyclictest0-21swapper/208:25:014
2795399204,12cyclictest0-21swapper/010:20:010
2795399203,12cyclictest0-21swapper/010:05:000
2795399203,12cyclictest0-21swapper/010:00:010
2795399203,12cyclictest0-21swapper/008:00:000
2801599193,11cyclictest0-21swapper/1011:50:012
2801599193,11cyclictest0-21swapper/1011:50:002
2800299194,11cyclictest0-21swapper/812:05:0110
2800299194,11cyclictest0-21swapper/812:05:0010
2800299193,12cyclictest0-21swapper/808:30:0110
27983991917,1cyclictest4634-21turbostat09:14:547
2795399194,12cyclictest0-21swapper/007:25:010
27953991913,5cyclictest0-21swapper/011:05:580
2795399190,18cyclictest0-21swapper/011:55:580
2795399190,18cyclictest0-21swapper/011:55:570
283702180,1sleep00-21swapper/012:04:380
283702180,1sleep00-21swapper/012:04:370
2801999183,11cyclictest0-21swapper/1110:40:013
2801999180,17cyclictest0-21swapper/1111:26:283
2800299183,11cyclictest0-21swapper/812:15:0110
2800299183,11cyclictest0-21swapper/812:15:0010
2800299182,12cyclictest0-21swapper/810:45:0110
2800299181,12cyclictest0-21swapper/810:30:0010
2799599184,10cyclictest0-21swapper/711:28:069
2799599181,14cyclictest0-21swapper/712:13:209
2799599181,14cyclictest0-21swapper/712:13:199
2798399183,11cyclictest0-21swapper/509:25:017
2798399183,11cyclictest0-21swapper/508:15:027
2798399183,10cyclictest0-21swapper/512:35:007
2798399183,10cyclictest0-21swapper/508:25:007
27983991816,1cyclictest69-21ksoftirqd/511:57:277
27983991816,1cyclictest69-21ksoftirqd/511:57:267
27983991816,1cyclictest69-21ksoftirqd/511:00:047
2796599183,11cyclictest0-21swapper/210:25:014
27965991815,2cyclictest36-21ksoftirqd/211:29:534
2801999174,10cyclictest0-21swapper/1111:10:003
2801999173,10cyclictest0-21swapper/1107:20:003
2801999172,11cyclictest0-21swapper/1108:30:003
28019991712,4cyclictest0-21swapper/1111:56:443
28019991712,4cyclictest0-21swapper/1111:56:433
27983991713,3cyclictest0-21swapper/511:19:057
2798399171,15cyclictest0-21swapper/512:30:147
2796599173,10cyclictest0-21swapper/207:40:014
2795399172,11cyclictest0-21swapper/007:30:000
27953991714,2cyclictest20543-21turbostat07:50:000
27953991712,4cyclictest0-21swapper/012:30:570
2795399171,15cyclictest0-21swapper/010:58:450
2795399171,15cyclictest0-21swapper/010:05:540
27953991710,5cyclictest0-21swapper/010:54:310
2801999163,10cyclictest0-21swapper/1111:20:013
2801999163,10cyclictest0-21swapper/1110:00:013
2801599163,10cyclictest0-21swapper/1011:30:002
2800899160,15cyclictest0-21swapper/912:32:4311
2798399163,9cyclictest0-21swapper/509:29:597
2798399161,3cyclictest0-21swapper/508:15:007
2798399160,15cyclictest0-21swapper/512:21:267
2798399160,15cyclictest0-21swapper/511:52:047
2798399160,15cyclictest0-21swapper/511:52:037
2798399160,15cyclictest0-21swapper/511:39:567
2798399160,15cyclictest0-21swapper/511:12:357
2796099161,14cyclictest0-21swapper/111:47:111
2796099161,14cyclictest0-21swapper/111:47:101
27953991613,2cyclictest15320-21ntp_states11:10:190
2795399161,14cyclictest0-21swapper/011:54:450
2795399161,14cyclictest0-21swapper/011:54:440
2795399160,15cyclictest0-21swapper/012:24:580
2795399160,15cyclictest0-21swapper/012:06:070
2795399160,15cyclictest0-21swapper/012:06:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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