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2022-05-29 - 01:25

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot1.osadl.org (updated Sat May 28, 2022 12:48:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3954991210,115rtkit-daemon0-21swapper/407:06:166
1605421180,0sleep111341ktimersoftd/1110:32:513
2952428172,6sleep110-21swapper/1107:07:153
2962727666,7sleep50-21swapper/507:08:457
2964427161,7sleep90-21swapper/907:09:0111
2955527163,6sleep10-21swapper/107:07:411
2954727061,6sleep60-21swapper/607:07:348
207632700,0sleep111341ktimersoftd/1111:54:003
2955126947,7sleep100-21swapper/1007:07:382
2962526858,7sleep30-21swapper/307:08:435
2968426555,7sleep80-21swapper/807:09:3610
2944526152,6sleep20-21swapper/207:06:054
2970926042,7sleep00-21swapper/007:09:520
2892126051,6sleep70-21swapper/707:05:229
129022580,1sleep40-21swapper/407:30:226
217952550,1sleep30-21swapper/311:55:285
279962510,1sleep30-21swapper/312:09:545
152702400,1sleep7105250irq/36-p5p1-TxR11:41:079
3019899310,30cyclictest0-21swapper/208:10:224
30198992622,3cyclictest0-21swapper/211:02:044
30187992521,3cyclictest0-21swapper/010:37:260
3018799250,24cyclictest0-21swapper/010:53:510
30256992421,2cyclictest0-21swapper/1111:03:313
30233992421,2cyclictest0-21swapper/710:54:089
3023399241,22cyclictest0-21swapper/708:29:579
30226992420,3cyclictest0-21swapper/610:38:098
3019899240,23cyclictest0-21swapper/210:54:254
3022699234,13cyclictest0-21swapper/607:34:378
3022099234,15cyclictest0-21swapper/512:10:007
30198992319,3cyclictest0-21swapper/210:55:344
30187992319,3cyclictest0-21swapper/010:43:300
30256992218,3cyclictest0-21swapper/1112:10:273
3025699220,21cyclictest0-21swapper/1111:17:443
30238992220,2cyclictest0-21swapper/811:47:2810
30238992220,2cyclictest0-21swapper/811:10:2110
30238992220,2cyclictest0-21swapper/810:57:5810
3022099220,21cyclictest0-21swapper/507:50:247
30187992218,3cyclictest0-21swapper/011:44:180
3018799220,21cyclictest0-21swapper/012:03:250
3018799220,21cyclictest0-21swapper/011:58:320
30256992117,3cyclictest0-21swapper/1111:46:113
30238992119,2cyclictest0-21swapper/811:56:2610
30238992117,3cyclictest0-21swapper/810:48:1810
3022699214,12cyclictest0-21swapper/612:30:008
3022699210,20cyclictest0-21swapper/611:14:188
30220992117,3cyclictest0-21swapper/511:36:467
3022099210,20cyclictest0-21swapper/511:11:097
3019899210,20cyclictest0-21swapper/208:57:164
3018799213,14cyclictest0-21swapper/008:50:010
30187992117,3cyclictest0-21swapper/011:10:430
30256992016,3cyclictest0-21swapper/1111:42:073
30256992016,3cyclictest0-21swapper/1111:14:123
3025699200,19cyclictest0-21swapper/1110:05:003
30238992017,2cyclictest0-21swapper/811:32:0310
30238992016,3cyclictest0-21swapper/811:08:2210
3022699204,12cyclictest0-21swapper/609:55:018
3022699204,12cyclictest0-21swapper/608:35:018
3022699204,11cyclictest0-21swapper/608:45:018
3022699203,12cyclictest0-21swapper/610:30:008
3022699203,12cyclictest0-21swapper/607:20:018
3022699200,19cyclictest0-21swapper/611:53:428
30198992016,3cyclictest0-21swapper/212:19:054
30187992018,1cyclictest3-21ksoftirqd/012:07:090
3018799200,19cyclictest0-21swapper/011:36:110
3022699194,11cyclictest0-21swapper/608:55:018
3022699193,11cyclictest0-21swapper/608:15:018
3022099194,12cyclictest0-21swapper/507:30:017
30220991915,3cyclictest0-21swapper/511:42:277
3022099190,18cyclictest0-21swapper/511:55:577
30192991915,3cyclictest0-21swapper/111:59:181
30192991915,3cyclictest0-21swapper/111:50:291
30187991915,3cyclictest0-21swapper/012:22:030
173052190,1sleep30-21swapper/311:45:275
30256991814,3cyclictest0-21swapper/1112:21:423
30256991814,3cyclictest0-21swapper/1110:57:423
3025699180,3cyclictest0-21swapper/1112:01:003
3025699180,12cyclictest0-21swapper/1112:08:253
3025699180,11cyclictest0-21swapper/1108:03:363
3024599180,17cyclictest0-21swapper/912:06:3611
30238991815,2cyclictest0-21swapper/812:01:2910
30238991815,2cyclictest0-21swapper/811:27:0710
30238991815,2cyclictest0-21swapper/811:21:3010
30238991815,2cyclictest0-21swapper/811:15:4510
3023899180,17cyclictest0-21swapper/810:51:4210
3023399180,17cyclictest0-21swapper/711:31:529
3022699184,9cyclictest0-21swapper/608:10:018
30226991815,2cyclictest0-21swapper/612:02:528
30226991814,3cyclictest0-21swapper/610:55:068
3022699180,17cyclictest0-21swapper/610:34:528
3022099183,11cyclictest0-21swapper/512:40:007
3022099183,11cyclictest0-21swapper/512:10:007
3022099183,11cyclictest0-21swapper/507:25:007
3022099180,17cyclictest0-21swapper/511:34:047
3022099180,17cyclictest0-21swapper/511:25:597
3021699180,17cyclictest0-21swapper/411:07:136
3021699180,17cyclictest0-21swapper/411:00:446
30198991814,3cyclictest0-21swapper/211:41:584
30198991814,3cyclictest0-21swapper/211:34:024
3019899180,17cyclictest0-21swapper/212:12:414
3019899180,17cyclictest0-21swapper/210:35:434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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