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2022-08-11 - 17:41

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rackcslot1.osadl.org (updated Thu Aug 11, 2022 12:48:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3954991030,98rtkit-daemon0-21swapper/1107:05:033
2040927667,6sleep40-21swapper/407:09:206
306442730,1sleep00-21swapper/012:15:190
2024527364,6sleep50-21swapper/507:06:587
2031427162,6sleep30-21swapper/307:07:555
238812700,1sleep90-21swapper/911:30:2211
175392700,1sleep70-21swapper/709:30:309
2025426859,7sleep10-21swapper/107:07:061
1835326854,7sleep90-21swapper/907:05:1211
2025926758,6sleep60-21swapper/607:07:108
2020726657,6sleep80-21swapper/807:06:2410
1870426452,6sleep100-21swapper/1007:05:132
128872640,2sleep80-21swapper/810:04:5910
124962620,1sleep100-21swapper/1011:18:112
2019325950,6sleep70-21swapper/707:06:119
2018825950,6sleep20-21swapper/207:06:064
148732590,1sleep70-21swapper/708:45:019
110962590,1sleep10-21swapper/110:00:281
192982580,0sleep50-21swapper/512:03:237
2039225646,7sleep00-21swapper/007:09:040
162422520,1sleep30-21swapper/311:21:275
20960992925,3cyclictest0-21swapper/1110:55:003
20960992824,3cyclictest0-21swapper/1110:44:173
20943992824,3cyclictest0-21swapper/911:46:2011
2088999280,27cyclictest0-21swapper/010:35:480
20943992723,3cyclictest0-21swapper/911:42:1611
2092599274,16cyclictest0-21swapper/611:05:018
2090199270,26cyclictest0-21swapper/212:09:284
20889992723,3cyclictest0-21swapper/012:27:410
20889992723,3cyclictest0-21swapper/012:27:400
2091399260,2cyclictest14498-21scp11:57:246
20895992622,3cyclictest0-21swapper/111:05:171
20952992522,3cyclictest0-21swapper/1012:23:362
20952992522,3cyclictest0-21swapper/1012:23:352
20937992521,3cyclictest0-21swapper/807:18:4810
2091399250,24cyclictest0-21swapper/411:08:316
20889992521,3cyclictest0-21swapper/010:48:030
20952992421,3cyclictest0-21swapper/1011:59:442
20952992420,3cyclictest0-21swapper/1011:32:562
20943992421,2cyclictest0-21swapper/911:57:4611
2094399240,23cyclictest0-21swapper/911:28:1111
20931992420,3cyclictest0-21swapper/711:05:029
20925992420,3cyclictest0-21swapper/611:02:548
2092599240,23cyclictest0-21swapper/612:18:508
2090199244,13cyclictest0-21swapper/210:12:414
2090199240,23cyclictest0-21swapper/210:34:034
2089599240,23cyclictest0-21swapper/111:13:481
20889992420,3cyclictest0-21swapper/011:25:310
2095299230,3cyclictest0-21swapper/1008:33:452
2093799230,22cyclictest0-21swapper/811:58:0510
2091399230,2cyclictest0-21swapper/410:56:596
2090199235,13cyclictest0-21swapper/207:15:004
2090199233,14cyclictest0-21swapper/212:30:014
2090199233,14cyclictest0-21swapper/212:30:004
20889992319,3cyclictest0-21swapper/011:43:000
269462220,2sleep20-21swapper/208:10:154
2096099223,12cyclictest0-21swapper/1112:10:013
20960992219,2cyclictest0-21swapper/1112:22:513
20960992219,2cyclictest0-21swapper/1112:22:503
20960992218,3cyclictest0-21swapper/1112:03:283
20960992218,3cyclictest0-21swapper/1110:57:573
20960992218,3cyclictest0-21swapper/1110:32:123
20943992219,2cyclictest0-21swapper/912:06:0611
2094399220,21cyclictest0-21swapper/911:22:0511
20937992219,2cyclictest102350irq/29-p34p109:37:0810
20937992215,6cyclictest102350irq/29-p34p109:23:4710
2093799220,14cyclictest0-21swapper/809:19:4810
20925992218,3cyclictest0-21swapper/612:23:328
20925992218,3cyclictest0-21swapper/612:23:318
2092099220,21cyclictest0-21swapper/511:54:497
20913992219,2cyclictest0-21swapper/411:12:206
2091399220,21cyclictest0-21swapper/407:57:396
2096099210,19cyclictest0-21swapper/1110:38:263
20952992118,2cyclictest29742-21diskmemload10:30:122
20952992117,3cyclictest0-21swapper/1012:28:512
20952992117,3cyclictest0-21swapper/1012:28:502
20937992117,3cyclictest0-21swapper/812:03:0610
2093199214,12cyclictest0-21swapper/707:45:019
20931992117,1cyclictest81rcu_preempt09:50:199
2092599213,13cyclictest0-21swapper/612:40:018
2092599213,13cyclictest0-21swapper/612:40:008
2092599213,12cyclictest0-21swapper/611:10:008
20925992117,3cyclictest0-21swapper/611:48:238
20925992117,3cyclictest0-21swapper/610:48:288
2092599210,20cyclictest0-21swapper/610:31:008
2092099214,12cyclictest0-21swapper/510:45:017
20920992117,3cyclictest0-21swapper/510:39:447
2091399210,20cyclictest0-21swapper/410:52:156
20895992119,1cyclictest25-21ksoftirqd/107:17:561
20895992118,2cyclictest0-21swapper/111:48:091
2089599210,20cyclictest0-21swapper/112:22:351
2089599210,20cyclictest0-21swapper/112:22:341
20952992017,2cyclictest0-21swapper/1011:10:482
20943992016,3cyclictest0-21swapper/911:00:5411
20943992016,3cyclictest0-21swapper/910:35:1511
2093799200,19cyclictest0-21swapper/812:29:5610
2093799200,19cyclictest0-21swapper/812:29:5510
2093199204,12cyclictest0-21swapper/711:30:009
2093199203,13cyclictest0-21swapper/708:05:019
20931992017,2cyclictest0-21swapper/711:10:269
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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