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2023-03-27 - 00:45

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rackcslot1.osadl.org (updated Sun Mar 26, 2023 12:48:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
390799970,91rtkit-daemon0-21swapper/807:07:4010
1951228777,8sleep110-21swapper/1107:10:003
1947728169,8sleep50-21swapper/507:09:317
1919927667,6sleep30-21swapper/307:05:415
1947627462,8sleep40-21swapper/407:09:296
1943726958,7sleep90-21swapper/907:08:5811
1949526859,6sleep100-21swapper/1007:09:482
1932726858,7sleep60-21swapper/607:07:318
1940226758,6sleep20-21swapper/207:08:284
1928026454,7sleep00-21swapper/007:06:490
1922626443,6sleep10-21swapper/107:06:031
179132640,0sleep111341ktimersoftd/1111:48:073
1937026252,7sleep70-21swapper/707:08:099
107512570,1sleep10-21swapper/111:37:201
2002099304,19cyclictest0-21swapper/811:25:0110
1998099265,14cyclictest0-21swapper/211:15:014
1998099264,14cyclictest0-21swapper/210:30:014
2000799244,14cyclictest0-21swapper/609:50:018
1999299234,14cyclictest0-21swapper/412:35:016
1998099235,14cyclictest0-21swapper/210:15:004
1998099235,13cyclictest0-21swapper/210:35:014
1998099234,14cyclictest0-21swapper/209:05:014
2001399223,13cyclictest0-21swapper/708:15:029
2000799224,14cyclictest0-21swapper/612:40:028
2000799224,13cyclictest0-21swapper/610:40:008
2000799224,13cyclictest0-21swapper/609:40:028
1999299220,15cyclictest0-21swapper/412:40:016
1998099224,12cyclictest0-21swapper/209:30:014
1997599224,13cyclictest0-21swapper/111:25:011
1997599223,14cyclictest0-21swapper/112:25:021
1996899224,13cyclictest0-21swapper/009:40:020
2002099213,13cyclictest0-21swapper/811:25:0110
1999299213,13cyclictest0-21swapper/412:00:016
1998099214,13cyclictest0-21swapper/210:55:014
1998099214,13cyclictest0-21swapper/208:55:014
1998099213,13cyclictest0-21swapper/208:00:014
1996899213,13cyclictest0-21swapper/009:25:010
1996899213,12cyclictest0-21swapper/012:15:010
2001399203,12cyclictest0-21swapper/709:15:019
2001399203,11cyclictest0-21swapper/711:25:019
2000799203,12cyclictest0-21swapper/610:15:008
1998099203,12cyclictest0-21swapper/207:35:014
1997599203,13cyclictest0-21swapper/108:50:011
1997599202,13cyclictest0-21swapper/107:25:021
1997599202,13cyclictest0-21swapper/107:25:011
2003099194,12cyclictest0-21swapper/1012:15:022
2000799193,13cyclictest0-21swapper/610:10:008
1998099193,12cyclictest0-21swapper/210:45:014
1998099193,12cyclictest0-21swapper/208:30:024
1997599193,13cyclictest0-21swapper/112:25:001
1997599191,13cyclictest0-21swapper/109:10:021
1996899192,11cyclictest0-21swapper/008:35:010
264192180,1sleep50-21swapper/511:13:107
219302180,1sleep80-21swapper/811:51:2910
20013991816,2cyclictest0-21swapper/712:05:019
1999299182,12cyclictest20250irq/28-ahci[00007:20:026
1999299182,12cyclictest20250irq/28-ahci[00007:20:026
1997599185,9cyclictest0-21swapper/111:15:011
2002099173,9cyclictest0-21swapper/812:20:0110
20020991712,4cyclictest0-21swapper/812:12:4810
2000799171,10cyclictest0-21swapper/612:30:028
1998099173,9cyclictest0-21swapper/211:05:014
1997599174,9cyclictest0-21swapper/110:15:011
1997599173,11cyclictest0-21swapper/112:35:001
1997599173,11cyclictest0-21swapper/112:20:011
2003099162,10cyclictest0-21swapper/1007:20:012
2003099162,10cyclictest0-21swapper/1007:20:012
2001399169,4cyclictest0-21swapper/711:52:369
2000799161,11cyclictest0-21swapper/609:25:018
2000799160,1cyclictest81rcu_preempt11:14:548
1997599163,10cyclictest0-21swapper/111:50:001
1997599162,11cyclictest0-21swapper/109:45:021
1996899164,11cyclictest0-21swapper/011:20:010
2003799150,14cyclictest0-21swapper/1111:40:003
2003099153,9cyclictest0-21swapper/1009:25:022
2003099152,9cyclictest0-21swapper/1009:45:022
2002099150,14cyclictest0-21swapper/812:38:5910
2001399152,9cyclictest0-21swapper/711:00:589
2001399151,13cyclictest0-21swapper/711:26:289
2001399150,14cyclictest0-21swapper/712:16:549
2001399150,14cyclictest0-21swapper/710:53:529
2001399150,14cyclictest0-21swapper/710:32:069
1999299152,9cyclictest0-21swapper/408:20:016
1999299150,14cyclictest0-21swapper/409:13:526
1998699150,14cyclictest0-21swapper/312:16:195
1998699150,14cyclictest0-21swapper/311:22:415
1997599153,9cyclictest0-21swapper/108:30:021
1997599150,14cyclictest0-21swapper/112:11:331
1996899151,13cyclictest0-21swapper/011:54:560
390799140,2rtkit-daemon0-21swapper/210:41:0710
2003799140,13cyclictest0-21swapper/1111:24:193
2003799140,13cyclictest0-21swapper/1107:55:573
2003799140,13cyclictest0-21swapper/1107:46:513
2003099143,8cyclictest0-21swapper/1011:45:002
2003099143,8cyclictest0-21swapper/1011:00:002
20030991410,3cyclictest0-21swapper/1011:45:192
2003099140,13cyclictest0-21swapper/1012:34:432
2003099140,13cyclictest0-21swapper/1011:01:492
2003099140,13cyclictest0-21swapper/1008:49:572
20024991410,3cyclictest0-21swapper/912:13:3511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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