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2023-11-28 - 20:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot1.osadl.org (updated Tue Nov 28, 2023 00:48:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
390799980,92rtkit-daemon0-21swapper/919:06:0811
170532930,1sleep60-21swapper/622:02:548
170532930,1sleep60-21swapper/622:02:538
97492820,2sleep80-21swapper/823:41:3210
2616627970,6sleep110-21swapper/1119:07:373
2609127465,6sleep100-21swapper/1019:06:362
2606627260,8sleep00-21swapper/019:06:140
157462710,1sleep40-21swapper/400:25:326
35412690,0sleep40-21swapper/419:20:316
2622626758,6sleep60-21swapper/619:08:338
2382526757,7sleep40-21swapper/419:05:056
2619726657,6sleep30-21swapper/319:08:065
2607126657,6sleep50-21swapper/519:06:187
2400526656,7sleep80-21swapper/819:05:2110
214672660,1sleep60-21swapper/622:08:068
214672660,1sleep60-21swapper/622:08:068
2625026543,7sleep20-21swapper/219:08:524
2620826556,6sleep10-21swapper/119:08:151
49852620,0sleep50-21swapper/500:15:087
2382826253,6sleep70-21swapper/719:05:089
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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