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2024-12-09 - 20:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Mon Dec 09, 2024 13:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3216:13:529084
16,16:13:219083
36,16:13:219082
32,16:13:219081
33,16:13:219080
33,16:13:219079
30,16:13:219078
17,16:13:219077
34,16:13:219076
36,16:13:219075
29,16:13:219074
31,16:13:219073
016:13:219069
0,16:13:219068
0,16:13:219067
0,16:13:219066
0,16:13:219065
0,16:13:219064
0,16:13:219063
0,16:13:219062
0,16:13:219061
0,16:13:219060
0,16:13:219059
0,16:13:219058
0,16:13:219057
0,16:13:219056
0,16:13:219055
0,16:13:219054
0,16:13:219053
0,16:13:219052
0,16:13:219051
0,16:13:219050
0,16:13:219049
0,16:13:219048
0,16:13:219047
0,16:13:219046
0,16:13:219045
0,16:13:219044
0,16:13:219043
0,16:13:219042
0,16:13:219041
0,16:13:219040
0,16:13:219039
0,16:13:219038
0,16:13:219037
0,16:13:219036
0,16:13:219035
0,16:13:219034
0,16:13:219033
0,16:13:219032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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