You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-06-27 - 16:32

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Mon Jun 27, 2022 12:48:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3954991020,93rtkit-daemon0-21swapper/707:08:249
2233927664,8sleep60-21swapper/607:06:098
2118527561,6sleep30-21swapper/307:05:185
2249327363,7sleep90-21swapper/907:08:2511
2243927358,12sleep100-21swapper/1007:07:382
2254026960,6sleep40-21swapper/407:09:086
2246726960,6sleep110-21swapper/1107:08:033
2245626960,6sleep10-21swapper/107:07:531
2242426947,7sleep80-21swapper/807:07:2410
2247426556,6sleep50-21swapper/507:08:097
2118426454,6sleep20-21swapper/207:05:174
322822620,8sleep11104950irq/33-p5p1-TxR10:58:443
153582600,0sleep50-21swapper/511:15:167
149182600,0sleep1014279-21ssh12:25:172
139812600,1sleep60-21swapper/610:00:208
2229425646,7sleep00-21swapper/007:05:270
262022530,3sleep72311799cyclictest12:03:119
2309099300,22cyclictest0-21swapper/308:52:305
23134992925,3cyclictest0-21swapper/1012:20:092
2311799290,27cyclictest0-21swapper/712:24:239
2307299280,27cyclictest0-21swapper/007:24:230
23130992723,3cyclictest0-21swapper/911:56:2711
23112992723,3cyclictest0-21swapper/612:04:288
2309099270,26cyclictest0-21swapper/312:18:105
23130992622,3cyclictest0-21swapper/911:51:3911
23140992521,3cyclictest0-21swapper/1110:35:223
23134992521,3cyclictest0-21swapper/1011:23:282
23130992521,3cyclictest0-21swapper/912:12:5611
2309099255,14cyclictest0-21swapper/311:55:015
2314099240,23cyclictest0-21swapper/1112:35:553
2311799240,23cyclictest0-21swapper/712:30:239
23112992420,3cyclictest0-21swapper/612:27:188
23078992421,2cyclictest0-21swapper/111:47:301
23078992420,3cyclictest0-21swapper/111:41:491
23072992420,3cyclictest0-21swapper/011:12:470
23072992420,3cyclictest0-21swapper/010:55:540
2307299240,23cyclictest0-21swapper/011:09:540
23140992319,3cyclictest0-21swapper/1111:48:173
2314099230,22cyclictest0-21swapper/1112:13:213
2311799230,22cyclictest0-21swapper/707:29:489
23112992321,1cyclictest80-21ksoftirqd/612:32:588
2310099230,22cyclictest0-21swapper/411:13:086
2307899234,13cyclictest0-21swapper/108:55:001
23078992319,3cyclictest0-21swapper/111:50:231
23134992218,3cyclictest0-21swapper/1012:18:322
23130992218,3cyclictest0-21swapper/911:00:0011
2311799225,13cyclictest0-21swapper/709:20:019
23105992219,2cyclictest0-21swapper/511:00:377
23105992219,2cyclictest0-21swapper/508:54:227
23105992218,3cyclictest0-21swapper/512:34:137
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional