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2023-01-30 - 05:31

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Mon Jan 30, 2023 00:48:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2019421100,1sleep80-21swapper/800:21:3110
390799990,89rtkit-daemon0-21swapper/419:07:366
2132527768,6sleep110-21swapper/1119:07:233
2147727464,7sleep30-21swapper/319:09:395
2012027259,6sleep90-21swapper/919:05:2011
2133226951,6sleep50-21swapper/519:07:287
2129026955,11sleep20-21swapper/219:06:494
2147126851,13sleep100-21swapper/1019:09:332
2146726757,7sleep60-21swapper/619:09:308
2126026555,7sleep00-21swapper/019:06:240
2136926455,6sleep10-21swapper/119:08:001
2149726246,7sleep80-21swapper/819:09:5710
2148326252,7sleep70-21swapper/719:09:429
292932600,0sleep110-21swapper/1122:15:193
292932600,0sleep110-21swapper/1122:15:193
323342560,1sleep50-21swapper/521:10:187
22492550,1sleep10-21swapper/100:36:371
104772490,1sleep3461ktimersoftd/300:11:255
2197499283,19cyclictest0-21swapper/123:00:011
2198199253,17cyclictest0-21swapper/222:35:014
2201999245,14cyclictest0-21swapper/823:30:0110
2201999245,14cyclictest0-21swapper/800:05:0110
2201999244,15cyclictest0-21swapper/821:30:0210
2201999244,14cyclictest0-21swapper/800:30:0110
2201399245,15cyclictest0-21swapper/723:55:019
2200799243,15cyclictest0-21swapper/620:10:028
2198199244,14cyclictest0-21swapper/222:10:024
2198199244,14cyclictest0-21swapper/222:10:014
2196899243,16cyclictest0-21swapper/023:45:010
22026992310,9cyclictest12129-21scp00:15:0311
2201999234,14cyclictest0-21swapper/819:45:0110
2201399234,14cyclictest0-21swapper/722:55:019
2198199234,13cyclictest0-21swapper/219:40:014
2198199234,13cyclictest0-21swapper/219:25:004
2196899234,14cyclictest0-21swapper/020:30:010
2201999224,14cyclictest0-21swapper/820:55:0210
2201999224,13cyclictest0-21swapper/822:40:0110
2198599223,13cyclictest0-21swapper/323:20:015
2198199224,13cyclictest0-21swapper/223:15:014
2196899223,15cyclictest0-21swapper/022:05:010
2196899223,14cyclictest0-21swapper/021:10:020
2202699214,13cyclictest0-21swapper/922:00:0211
2198599211,14cyclictest0-21swapper/300:20:015
2198199214,12cyclictest0-21swapper/222:05:014
2198199214,12cyclictest0-21swapper/220:45:004
2197499213,13cyclictest0-21swapper/100:05:011
2196899213,13cyclictest0-21swapper/020:55:020
2203099203,12cyclictest0-21swapper/1000:25:022
2202699204,13cyclictest0-21swapper/900:30:0211
2201999204,12cyclictest0-21swapper/821:10:0110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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