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2022-01-26 - 11:54

Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Wed Jan 26, 2022 00:48:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3954991140,108rtkit-daemon0-21swapper/419:09:436
1908928373,7sleep110-21swapper/1119:05:113
126882800,1sleep00-21swapper/023:10:310
2084127869,6sleep50-21swapper/519:05:547
231002760,1sleep60-21swapper/619:10:198
2149227465,6sleep80-21swapper/819:08:3410
2032227458,7sleep20-21swapper/219:05:274
228692720,1sleep20-21swapper/221:35:224
2153027260,8sleep70-21swapper/719:09:099
1996227161,6sleep90-21swapper/919:05:2111
2157526858,7sleep100-21swapper/1019:09:482
2152626757,6sleep30-21swapper/319:09:055
2041826750,7sleep60-21swapper/619:05:308
2156526252,7sleep00-21swapper/019:09:370
36212590,0sleep4561rcuc/419:30:196
2049425846,6sleep10-21swapper/119:05:381
56192550,1sleep50-21swapper/521:51:157
2204199244,14cyclictest0-21swapper/120:40:001
2208799213,12cyclictest0-21swapper/821:50:0010
2208799210,20cyclictest0-21swapper/822:19:1110
2208799210,13cyclictest0-21swapper/819:50:1510
2208799210,13cyclictest0-21swapper/819:50:1410
2204899214,12cyclictest0-21swapper/223:50:004
2204199213,13cyclictest0-21swapper/100:04:591
2204199211,19cyclictest0-21swapper/121:35:231
6202200,2sleep72208199cyclictest21:10:259
2209999203,12cyclictest0-21swapper/1022:30:002
2209999203,12cyclictest0-21swapper/1021:05:012
2209399204,11cyclictest0-21swapper/921:41:1111
2208799203,12cyclictest0-21swapper/800:34:5910
2208199204,11cyclictest0-21swapper/721:45:009
2208199203,13cyclictest0-21swapper/720:50:019
2206599204,11cyclictest0-21swapper/522:19:597
2206199204,12cyclictest0-21swapper/421:45:016
2210599190,18cyclictest0-21swapper/1123:44:553
2209399193,12cyclictest0-21swapper/900:20:0111
2209399193,11cyclictest0-21swapper/923:50:0111
2208799199,4cyclictest0-21swapper/821:55:0110
2208799197,3cyclictest0-21swapper/822:56:1310
2208799194,11cyclictest0-21swapper/820:55:0110
2208799190,10cyclictest0-21swapper/819:21:0910
2208199194,11cyclictest0-21swapper/721:30:019
2208199194,11cyclictest0-21swapper/720:50:009
2208199193,12cyclictest0-21swapper/719:55:019
2208199193,12cyclictest0-21swapper/719:55:019
2208199193,12cyclictest0-21swapper/719:25:009
2206199194,11cyclictest0-21swapper/421:05:016
2205499194,11cyclictest0-21swapper/319:25:015
2205499194,10cyclictest0-21swapper/322:15:005
2205499194,10cyclictest0-21swapper/319:35:015
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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