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2024-07-20 - 23:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Fri Jul 19, 2024 13:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3200:40:449084
16,00:40:139083
36,00:40:139082
32,00:40:139081
33,00:40:139080
33,00:40:139079
30,00:40:139078
17,00:40:139077
34,00:40:139076
36,00:40:139075
29,00:40:139074
31,00:40:139073
000:40:139069
0,00:40:139068
0,00:40:139067
0,00:40:139066
0,00:40:139065
0,00:40:139064
0,00:40:139063
0,00:40:139062
0,00:40:139061
0,00:40:139060
0,00:40:139059
0,00:40:139058
0,00:40:139057
0,00:40:139056
0,00:40:139055
0,00:40:139054
0,00:40:139053
0,00:40:139052
0,00:40:139051
0,00:40:139050
0,00:40:139049
0,00:40:139048
0,00:40:139047
0,00:40:139046
0,00:40:139045
0,00:40:139044
0,00:40:139043
0,00:40:139042
0,00:40:139041
0,00:40:139040
0,00:40:139039
0,00:40:139038
0,00:40:139037
0,00:40:139036
0,00:40:139035
0,00:40:139034
0,00:40:139033
0,00:40:139032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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