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2023-06-05 - 21:41

x86 Intel Core i7-X990 @3467 MHz, Linux 4.9.47-rt37 (Profile)

Latency plot of system in rack #c, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot1.osadl.org (updated Mon Jun 05, 2023 12:48:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
376211852,6sleep90-21swapper/907:06:5911
390799910,81rtkit-daemon0-21swapper/607:09:198
390799800,70rtkit-daemon0-21swapper/007:05:210
44527767,7sleep110-21swapper/1107:08:003
48127252,6sleep50-21swapper/507:08:307
32827263,6sleep30-21swapper/307:06:175
41626455,6sleep100-21swapper/1007:07:362
31426455,6sleep20-21swapper/207:06:034
31926354,6sleep70-21swapper/707:06:089
30226051,6sleep40-21swapper/407:05:536
248702580,1sleep110-21swapper/1112:09:483
56325647,6sleep80-21swapper/807:09:3310
33925647,6sleep10-21swapper/107:06:261
109399273,17cyclictest0-21swapper/212:25:014
109399235,13cyclictest0-21swapper/210:40:014
109399233,14cyclictest0-21swapper/208:10:014
106799233,16cyclictest0-21swapper/011:40:180
114699211,19cyclictest0-21swapper/1108:15:263
112799214,13cyclictest0-21swapper/811:00:0110
111099204,12cyclictest0-21swapper/511:15:027
111099204,12cyclictest0-21swapper/509:15:017
111099203,14cyclictest0-21swapper/512:35:017
111099203,11cyclictest0-21swapper/509:25:017
1067992010,6cyclictest5109-1kworker/0:2H07:45:020
112799195,10cyclictest0-21swapper/811:45:0010
112799194,11cyclictest0-21swapper/809:20:0110
112799194,10cyclictest0-21swapper/811:25:0110
112799194,10cyclictest0-21swapper/810:35:0110
112799192,13cyclictest0-21swapper/809:25:0110
112799191,13cyclictest0-21swapper/810:25:0110
112799191,12cyclictest0-21swapper/811:30:0110
111099193,11cyclictest0-21swapper/509:25:017
111099193,11cyclictest0-21swapper/508:40:017
110499194,12cyclictest0-21swapper/409:25:026
109399193,11cyclictest0-21swapper/208:30:024
109399192,12cyclictest0-21swapper/211:10:034
114099180,17cyclictest0-21swapper/1011:56:422
112799183,11cyclictest0-21swapper/810:45:0110
112799183,11cyclictest0-21swapper/809:55:0210
111599183,11cyclictest0-21swapper/610:10:018
111099184,11cyclictest0-21swapper/508:20:027
111099183,11cyclictest0-21swapper/507:35:017
109399183,11cyclictest0-21swapper/208:25:024
109399183,10cyclictest0-21swapper/210:20:014
106799183,10cyclictest0-21swapper/010:15:010
114699173,9cyclictest0-21swapper/1111:40:003
114099173,9cyclictest0-21swapper/1007:40:012
112299170,16cyclictest0-21swapper/712:11:119
111599173,11cyclictest0-21swapper/610:30:018
111599173,11cyclictest0-21swapper/608:00:028
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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