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2024-07-27 - 03:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Jul 26, 2024 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3144927952,22sleep10-21swapper/107:02:121
3149427663,8sleep00-21swapper/007:02:390
53492680,0sleep00-21swapper/011:44:360
183432200,0sleep10-21swapper/112:02:401
31827991616,0cyclictest27408-21ssh10:48:351
31827991615,1cyclictest1078-21ssh10:55:321
31826991615,1cyclictest14894-21ssh10:30:570
31826991610,5cyclictest0-21swapper/011:58:480
31826991610,4cyclictest0-21swapper/009:50:320
31827991515,0cyclictest0-21swapper/111:55:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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