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2026-01-25 - 12:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sun Jan 25, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2944127353,15sleep10-21swapper/119:08:381
46702690,1sleep00-21swapper/022:25:140
2855526633,5sleep00-21swapper/019:05:010
254482660,0sleep00-21swapper/021:27:570
29728993838,0cyclictest0-21swapper/020:57:150
29729993712,24cyclictest0-21swapper/122:59:211
29729993510,24cyclictest32155-21kworker/u4:200:00:351
29729993510,24cyclictest32155-21kworker/u4:200:00:351
29729993333,0cyclictest0-21swapper/122:49:561
29729992710,1cyclictest0-21swapper/121:20:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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