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2024-09-08 - 11:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sun Sep 08, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1631426854,9sleep10-21swapper/119:05:511
1631026451,8sleep00-21swapper/019:05:480
123272630,0sleep10-21swapper/122:15:101
16977993231,0cyclictest0-21swapper/121:47:501
16977992929,0cyclictest0-21swapper/123:54:591
16977992910,18cyclictest0-21swapper/122:32:441
16977992620,5cyclictest6116-21apache222:45:161
1697799260,3cyclictest32131-21/usr/sbin/munin00:20:111
16976992610,4cyclictest0-21swapper/022:41:170
16976992610,14cyclictest97850irq/107-eth1-rx22:46:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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