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2025-07-09 - 08:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Jul 09, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
42672920,1sleep00-21swapper/020:58:000
2591227057,8sleep00-21swapper/019:03:450
2585826956,8sleep10-21swapper/119:03:141
26476994110,30cyclictest0-21swapper/023:35:460
2647799342,5cyclictest24-21ksoftirqd/122:48:021
26476993410,2cyclictest0-21swapper/000:27:550
2647799334,3cyclictest91rcu_preempt21:07:501
26477993231,0cyclictest231ktimersoftd/120:43:071
26477993227,2cyclictest24-21ksoftirqd/121:42:471
2647799322,0cyclictest91rcu_preempt23:22:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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