You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-01-21 - 22:48
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue Jan 21, 2025 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
247882700,1sleep10-21swapper/111:45:251
131902690,1sleep013188-21timerandwakeup11:29:170
2172726855,8sleep10-21swapper/107:06:011
272672630,1sleep027263-21seq07:19:220
2026526349,9sleep00-21swapper/007:04:120
12482560,0sleep10-21swapper/111:57:231
9132480,0sleep10-21swapper/109:47:281
91942430,1sleep10-21swapper/109:14:181
22198993610,3cyclictest0-21swapper/110:50:551
22197993310,23cyclictest0-21swapper/009:09:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional