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2026-05-11 - 19:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon May 11, 2026 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139627058,8sleep00-21swapper/007:07:280
3217126552,8sleep10-21swapper/107:04:031
174602640,0sleep00-21swapper/011:54:130
1724993434,0cyclictest0-21swapper/111:06:581
1724992929,0cyclictest0-21swapper/109:26:221
1724992910,14cyclictest0-21swapper/108:34:081
1724992810,14cyclictest100250irq/107-eth1-rx11:18:041
1723992810,7cyclictest0-21swapper/011:00:210
1724992710,15cyclictest0-21swapper/111:02:291
172499270,22cyclictest0-21swapper/111:10:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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