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2023-12-08 - 23:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Fri Dec 08, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2439626855,8sleep00-21swapper/007:01:090
2583926754,9sleep10-21swapper/107:02:501
125162670,1sleep10-21swapper/111:10:561
2632199239,9cyclictest26396-21ssh11:28:021
26321992120,1cyclictest0-21swapper/109:45:131
26321992019,1cyclictest0-21swapper/112:03:381
26321992019,1cyclictest0-21swapper/111:49:241
26321992019,1cyclictest0-21swapper/111:19:281
26321992019,1cyclictest0-21swapper/110:36:491
26321992019,1cyclictest0-21swapper/109:31:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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