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2024-04-25 - 23:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Thu Apr 25, 2024 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128626957,8sleep10-21swapper/107:03:231
117332690,0sleep10-21swapper/110:25:271
116826956,8sleep00-21swapper/007:02:100
6092650,1sleep00-21swapper/011:41:330
259632620,2sleep1162199cyclictest11:31:121
1620991710,6cyclictest5049-21ssh11:00:350
1621991616,0cyclictest0-21swapper/108:50:181
1621991615,1cyclictest22186-21ls11:25:231
1621991610,6cyclictest0-21swapper/108:22:571
1621991610,0cyclictest0-21swapper/112:33:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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