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2025-07-12 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Sat Jul 12, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2958826847,17sleep10-21swapper/119:07:051
2929426754,8sleep00-21swapper/019:04:010
252142670,1sleep024405-21/usr/sbin/munin20:18:060
29832993636,0cyclictest0-21swapper/022:26:090
29832993210,21cyclictest0-21swapper/019:23:040
2983399300,0cyclictest0-21swapper/122:48:231
29832993010,14cyclictest0-21swapper/021:42:500
2983399290,22cyclictest5149-21/usr/sbin/munin19:28:021
29832992910,14cyclictest0-21swapper/022:33:230
29832992910,0cyclictest0-21swapper/022:06:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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