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2024-05-28 - 05:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Tue May 28, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2725827561,9sleep00-21swapper/019:04:020
2691526855,8sleep10-21swapper/119:00:301
235052680,1sleep00-21swapper/022:08:550
152502680,1sleep081ktimersoftd/021:14:330
140692680,0sleep10-21swapper/123:23:221
48732650,0sleep10-21swapper/123:54:571
269952180,0sleep10-21swapper/100:24:581
110772180,0sleep00-21swapper/022:35:140
27505991716,0cyclictest15803-21ssh21:58:271
27504991715,1cyclictest285802sleep000:26:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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