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2025-05-24 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot2.osadl.org (updated Sat May 24, 2025 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283327755,17sleep00-21swapper/019:05:400
295027360,9sleep10-21swapper/119:06:541
76502710,0sleep10-21swapper/121:37:441
153622670,0sleep00-21swapper/019:38:290
3252994410,33cyclictest0-21swapper/122:44:041
3252994410,28cyclictest0-21swapper/121:16:261
3252994310,32cyclictest0-21swapper/120:05:111
3252994210,31cyclictest23087-21ls19:58:271
3252994110,30cyclictest0-21swapper/100:01:551
3252994010,9cyclictest0-21swapper/122:17:071
3252993910,29cyclictest0-21swapper/123:56:021
3252993910,28cyclictest0-21swapper/123:49:211
3252993910,28cyclictest0-21swapper/123:39:541
3252993910,28cyclictest0-21swapper/120:35:161
3252993910,28cyclictest0-21swapper/119:38:091
3252993910,26cyclictest0-21swapper/122:08:261
3252993815,20cyclictest91rcu_preempt23:25:151
3252993810,28cyclictest0-21swapper/100:23:311
3252993810,27cyclictest0-21swapper/123:13:261
3252993810,27cyclictest0-21swapper/122:56:041
3252993810,27cyclictest0-21swapper/122:36:571
3252993810,27cyclictest0-21swapper/121:30:231
3252993810,27cyclictest0-21swapper/119:28:261
3252993810,26cyclictest0-21swapper/121:27:241
3252993810,25cyclictest0-21swapper/100:06:031
3252993810,16cyclictest0-21swapper/100:34:171
3252993710,26cyclictest0-21swapper/123:33:361
3252993710,26cyclictest0-21swapper/122:02:551
3252993710,26cyclictest0-21swapper/121:51:471
3252993611,24cyclictest0-21swapper/119:47:511
3252993611,24cyclictest0-21swapper/100:09:401
3252993610,26cyclictest0-21swapper/122:38:371
3252993610,25cyclictest0-21swapper/123:21:241
3252993610,25cyclictest0-21swapper/123:11:341
3252993610,25cyclictest0-21swapper/122:59:501
3252993610,25cyclictest0-21swapper/121:08:361
3252993610,25cyclictest0-21swapper/120:44:061
3252993610,24cyclictest0-21swapper/100:15:261
3252993610,20cyclictest9927-21ssh00:32:171
3252993512,22cyclictest0-21swapper/120:53:261
3252993510,25cyclictest0-21swapper/123:47:291
3252993510,24cyclictest0-21swapper/122:18:291
3252993510,24cyclictest0-21swapper/121:54:141
3252993510,24cyclictest0-21swapper/121:22:351
3252993510,24cyclictest0-21swapper/119:15:021
3252993510,22cyclictest0-21swapper/121:43:191
3252993416,17cyclictest0-21swapper/123:28:241
3252993411,17cyclictest91rcu_preempt19:22:331
3252993410,24cyclictest0-21swapper/100:18:111
3252993410,23cyclictest0-21swapper/121:38:321
3252993410,22cyclictest0-21swapper/122:29:181
3252993310,22cyclictest0-21swapper/119:13:041
3252993212,20cyclictest0-21swapper/119:53:111
3252993210,22cyclictest0-21swapper/122:03:261
3252993210,21cyclictest0-21swapper/122:48:301
3252993210,21cyclictest0-21swapper/122:23:211
3252993121,10cyclictest0-21swapper/123:06:071
3252993110,20cyclictest0-21swapper/120:14:031
3252993110,16cyclictest0-21swapper/120:38:241
3252993010,18cyclictest0-21swapper/119:23:221
3252992910,18cyclictest0-21swapper/120:10:151
3252992910,17cyclictest0-21swapper/120:28:311
3251992921,3cyclictest3249-21cyclictest23:18:240
3251992910,18cyclictest0-21swapper/020:27:280
3252992811,10cyclictest91rcu_preempt20:22:491
3252992810,18cyclictest0-21swapper/119:40:561
3252992810,15cyclictest0-21swapper/120:59:561
325299280,27cyclictest18873-21tune2fs19:48:241
325299280,27cyclictest0-21swapper/120:48:211
3251992810,15cyclictest0-21swapper/000:30:120
3252992710,16cyclictest0-21swapper/121:05:481
3251992710,8cyclictest0-21swapper/022:01:190
3251992710,0cyclictest0-21swapper/000:12:100
3251992510,6cyclictest0-21swapper/022:53:310
325199250,0cyclictest31969-21ssh22:51:480
3252992412,6cyclictest91rcu_preempt20:23:261
325199243,4cyclictest101rcu_sched19:33:090
3251992424,0cyclictest0-21swapper/019:18:210
3251992421,1cyclictest81ktimersoftd/019:11:110
3251992419,1cyclictest81ktimersoftd/020:53:270
3251992411,4cyclictest0-21swapper/020:03:220
3251992322,1cyclictest23828-21apache223:31:250
3251992322,0cyclictest0-21swapper/021:33:240
3251992321,1cyclictest7-21ksoftirqd/023:53:090
3251992315,2cyclictest21831-21ntp_states00:03:250
3251992310,7cyclictest0-21swapper/000:18:220
3251992310,1cyclictest0-21swapper/023:02:030
325199224,10cyclictest0-21swapper/000:33:260
3251992222,0cyclictest0-21swapper/023:38:350
325199222,19cyclictest0-21swapper/021:58:070
325199222,14cyclictest0-21swapper/023:06:270
3251992219,1cyclictest97750irq/106-eth1-rx23:08:270
3251992217,4cyclictest636-21nscd22:18:140
3251992212,4cyclictest23828-21apache223:33:150
3251992210,7cyclictest0-21swapper/022:25:240
3251992210,5cyclictest0-21swapper/021:18:210
325199220,21cyclictest20077-21ssh21:11:390
3251992120,1cyclictest0-21swapper/000:00:410
3251992110,8cyclictest0-21swapper/022:44:350
3251992110,7cyclictest0-21swapper/019:43:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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