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2023-02-06 - 20:37

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot2.osadl.org (updated Mon Feb 06, 2023 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314932780,0sleep0596-21lldpd07:53:000
65332730,0sleep1596-21lldpd10:52:431
246292220,1sleep1596-21lldpd09:50:081
13951992220,1cyclictest596-21lldpd12:17:061
13951992220,1cyclictest0-21swapper/111:48:461
13951992220,1cyclictest0-21swapper/110:53:431
13951992220,1cyclictest0-21swapper/110:27:571
13951992220,1cyclictest0-21swapper/108:44:461
13951992220,1cyclictest0-21swapper/108:34:471
13951992217,1cyclictest0-21swapper/108:26:311
13951992217,1cyclictest0-21swapper/108:03:321
13951992120,1cyclictest596-21lldpd09:28:501
13951992120,1cyclictest0-21swapper/110:15:391
13951992120,1cyclictest0-21swapper/109:38:451
13951992120,0cyclictest596-21lldpd09:06:031
13951992120,0cyclictest0-21swapper/109:53:161
13951992119,1cyclictest596-21lldpd12:29:171
13951992119,1cyclictest596-21lldpd12:24:561
13951992119,1cyclictest596-21lldpd11:28:391
13951992119,1cyclictest596-21lldpd11:25:051
13951992119,1cyclictest596-21lldpd10:42:401
13951992119,1cyclictest596-21lldpd10:10:591
13951992119,1cyclictest596-21lldpd08:53:471
13951992119,1cyclictest596-21lldpd08:41:041
13951992119,1cyclictest596-21lldpd08:18:071
13951992119,1cyclictest596-21lldpd07:46:091
13951992119,1cyclictest0-21swapper/112:33:351
13951992119,1cyclictest0-21swapper/112:21:491
13951992119,1cyclictest0-21swapper/112:09:231
13951992119,1cyclictest0-21swapper/112:06:281
13951992119,1cyclictest0-21swapper/111:59:191
13951992119,1cyclictest0-21swapper/111:47:121
13951992119,1cyclictest0-21swapper/111:42:301
13951992119,1cyclictest0-21swapper/111:42:301
13951992119,1cyclictest0-21swapper/111:08:511
13951992119,1cyclictest0-21swapper/111:06:111
13951992119,1cyclictest0-21swapper/110:59:581
13951992119,1cyclictest0-21swapper/110:44:571
13951992119,1cyclictest0-21swapper/110:30:281
13951992119,1cyclictest0-21swapper/110:19:571
13951992119,1cyclictest0-21swapper/110:03:301
13951992119,1cyclictest0-21swapper/109:58:481
13951992119,1cyclictest0-21swapper/109:44:331
13951992119,1cyclictest0-21swapper/109:22:591
13951992119,1cyclictest0-21swapper/109:13:421
13951992119,1cyclictest0-21swapper/109:08:451
13951992119,1cyclictest0-21swapper/108:48:491
13951992119,1cyclictest0-21swapper/108:15:141
13951992119,1cyclictest0-21swapper/107:53:331
13951992119,1cyclictest0-21swapper/107:50:361
13951992119,1cyclictest0-21swapper/107:40:511
13951992119,1cyclictest0-21swapper/107:26:121
13951992119,1cyclictest0-21swapper/107:13:561
13951992119,1cyclictest0-21swapper/107:10:051
13951992118,2cyclictest0-21swapper/110:34:431
13951992020,0cyclictest596-21lldpd09:35:351
13951992019,1cyclictest0-21swapper/111:33:011
13951992019,1cyclictest0-21swapper/111:19:271
13951992019,1cyclictest0-21swapper/111:13:251
13951992019,1cyclictest0-21swapper/109:23:101
13951992019,1cyclictest0-21swapper/108:58:251
13951992019,1cyclictest0-21swapper/108:08:041
13951992019,1cyclictest0-21swapper/107:58:421
13951992019,1cyclictest0-21swapper/107:18:201
13951992019,0cyclictest596-21lldpd07:33:211
13951992019,0cyclictest596-21lldpd07:31:591
13951992019,0cyclictest0-21swapper/111:53:111
66702190,0sleep00-21swapper/010:53:000
13951991919,0cyclictest596-21lldpd08:30:371
128162180,1sleep0596-21lldpd07:03:200
13933991715,1cyclictest240652sleep008:56:350
261792160,0sleep026178-21seq11:18:000
13933991610,5cyclictest0-21swapper/009:16:220
13933991610,3cyclictest730-21snmpd12:29:500
13933991514,0cyclictest7-21ksoftirqd/008:48:000
13933991514,0cyclictest17087-21ls07:13:280
13933991513,1cyclictest14431-21chrt08:32:070
13933991513,1cyclictest0-21swapper/012:22:110
13933991513,1cyclictest0-21swapper/009:53:530
13933991513,1cyclictest0-21swapper/009:35:170
13933991513,1cyclictest0-21swapper/007:45:040
13933991511,1cyclictest91rcu_preempt12:13:240
13933991510,0cyclictest25846-21kworker/0:009:19:010
13933991413,1cyclictest24982-21ls10:33:260
13933991413,0cyclictest7-21ksoftirqd/009:48:230
13933991413,0cyclictest7-21ksoftirqd/008:41:350
13933991413,0cyclictest7-21ksoftirqd/008:16:350
13933991412,1cyclictest7-21ksoftirqd/011:29:300
13933991412,1cyclictest7-21ksoftirqd/011:24:330
13933991412,1cyclictest596-21lldpd11:53:370
13933991412,1cyclictest158142sleep009:38:130
13933991412,1cyclictest0-21swapper/011:38:520
13933991412,1cyclictest0-21swapper/011:38:520
13933991412,1cyclictest0-21swapper/011:36:310
13933991412,1cyclictest0-21swapper/011:03:060
13933991412,1cyclictest0-21swapper/009:00:310
13933991412,1cyclictest0-21swapper/008:27:540
13933991412,1cyclictest0-21swapper/008:10:540
13933991412,1cyclictest0-21swapper/007:56:570
13933991411,2cyclictest730-21snmpd10:03:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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