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2023-12-02 - 19:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sat Dec 02, 2023 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
821527249,18sleep10-21swapper/107:02:421
33472690,1sleep081ktimersoftd/012:06:260
812426856,8sleep00-21swapper/007:01:440
201062680,0sleep00-21swapper/011:05:320
64272660,2sleep081ktimersoftd/012:11:090
320902490,0sleep00-21swapper/008:06:200
8719991816,1cyclictest26092-21sh11:54:571
8719991716,1cyclictest25543-21ssh10:30:081
8719991716,1cyclictest12127-21ssh10:12:421
8719991716,0cyclictest24-21ksoftirqd/109:50:591
8718991710,7cyclictest0-21swapper/012:29:500
8719991615,1cyclictest8271-21ssh10:50:531
8719991615,1cyclictest23185-21ssh11:08:351
8719991615,1cyclictest22448-21ssh09:44:551
8719991615,0cyclictest4114-21ssh12:06:441
8719991615,0cyclictest31850-21chrt08:05:291
8719991610,5cyclictest0-21swapper/110:37:461
8719991610,0cyclictest0-21swapper/112:35:531
8719991610,0cyclictest0-21swapper/108:59:081
8718991610,6cyclictest0-21swapper/010:26:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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