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2026-07-18 - 11:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sat Jul 18, 2026 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
283322740,1sleep1221rcuc/119:13:391
2563127158,8sleep10-21swapper/119:05:541
2572126854,9sleep00-21swapper/019:06:510
301092630,0sleep00-21swapper/019:18:340
26049993910,22cyclictest0-21swapper/021:14:300
26050993510,24cyclictest0-21swapper/121:44:451
26050993510,16cyclictest0-21swapper/122:54:371
26050993410,5cyclictest0-21swapper/120:33:391
26050993110,0cyclictest0-21swapper/122:38:541
2605099303,9cyclictest0-21swapper/123:29:331
2604999300,2cyclictest590-21rs:main0
2605099293,3cyclictest24841-21/usr/sbin/munin20:28:361
26050992915,13cyclictest26047-21cyclictest23:13:421
26050992910,10cyclictest0-21swapper/123:22:061
2604999290,26cyclictest0-21swapper/022:19:250
26050992814,12cyclictest636-21nscd23:05:101
26050992810,17cyclictest0-21swapper/123:49:101
2605099280,7cyclictest0-21swapper/123:02:381
2605099274,5cyclictest30209-21perf23:38:231
2605099272,4cyclictest3412-21ssh22:23:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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