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2024-07-21 - 21:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sun Jul 21, 2024 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3188827058,8sleep10-21swapper/107:01:251
3041126350,8sleep00-21swapper/006:59:230
242382620,0sleep10-21swapper/109:16:351
102042590,0sleep10-21swapper/108:54:281
25832220,0sleep00-21swapper/009:30:130
58062210,1sleep1231ktimersoftd/108:41:281
32349991810,8cyclictest0-21swapper/009:54:350
32349991716,1cyclictest4954-21ssh11:47:080
32350991615,0cyclictest4612-21chrt10:16:151
32350991614,1cyclictest14826-21ssh11:14:371
32350991610,6cyclictest0-21swapper/112:28:181
32350991610,6cyclictest0-21swapper/112:23:271
32350991610,6cyclictest0-21swapper/108:02:271
32350991610,6cyclictest0-21swapper/107:55:551
32350991610,1cyclictest0-21swapper/107:35:171
32350991610,0cyclictest0-21swapper/112:04:041
32349991616,0cyclictest29438-21ssh12:21:340
32350991515,0cyclictest0-21swapper/110:27:111
32350991515,0cyclictest0-21swapper/108:50:171
32350991513,1cyclictest20776-21/usr/sbin/munin11:24:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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