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2019-07-17 - 02:47

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
The worst-case latency is about 1.00 times higher under extreme CPU load.
Results of all systems under extreme CPU load are combined on this summary graph.
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Wed Jul 17, 2019 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2047926755,8sleep10-21swapper/119:05:551
2042926553,8sleep00-21swapper/019:05:230
200202200,0sleep10-21swapper/100:35:131
200202200,0sleep10-21swapper/100:35:131
21119991615,1cyclictest12625-21sshd21:31:431
21119991610,0cyclictest0-21swapper/123:41:411
21118991616,0cyclictest0-21swapper/023:30:120
21118991616,0cyclictest0-21swapper/000:31:000
21118991615,1cyclictest1442-21df23:50:060
21118991610,6cyclictest0-21swapper/023:59:340
21118991610,6cyclictest0-21swapper/023:48:460
21118991610,6cyclictest0-21swapper/023:41:220
21118991610,6cyclictest0-21swapper/023:37:180
21118991610,6cyclictest0-21swapper/022:51:220
21118991610,6cyclictest0-21swapper/022:20:120
21118991610,6cyclictest0-21swapper/022:18:180
21118991610,6cyclictest0-21swapper/021:13:080
21118991610,6cyclictest0-21swapper/020:57:440
21118991610,6cyclictest0-21swapper/019:48:280
21118991610,6cyclictest0-21swapper/019:25:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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