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2026-03-06 - 09:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Mar 06, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2570721960,2sleep00-21swapper/019:04:490
2618627057,9sleep10-21swapper/119:06:151
279452680,0sleep10-21swapper/123:48:531
317502630,1sleep131742-21fschecks_time22:24:411
315982550,0sleep00-21swapper/023:09:280
26675994110,31cyclictest0-21swapper/021:21:510
26675994110,30cyclictest0-21swapper/021:41:320
26675994110,29cyclictest0-21swapper/000:20:290
26676994010,0cyclictest0-21swapper/120:47:221
26675993911,27cyclictest7908-21diskmemload22:08:320
26675993910,29cyclictest0-21swapper/023:59:400
26675993910,28cyclictest0-21swapper/021:53:410
26675993910,28cyclictest0-21swapper/019:47:210
26675993910,22cyclictest0-21swapper/023:22:080
26675993810,27cyclictest0-21swapper/023:02:260
26675993810,27cyclictest0-21swapper/022:16:460
26675993810,27cyclictest0-21swapper/021:28:210
26675993810,26cyclictest0-21swapper/021:34:480
26675993810,22cyclictest91rcu_preempt22:14:000
26675993710,27cyclictest0-21swapper/023:44:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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