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2023-06-08 - 23:57

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Thu Jun 08, 2023 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
443526654,8sleep00-21swapper/007:03:010
442426655,7sleep10-21swapper/107:02:541
5023991717,0cyclictest0-21swapper/111:27:431
5022991710,0cyclictest0-21swapper/010:45:260
1408221710,2sleep00-21swapper/011:37:430
5023991610,0cyclictest0-21swapper/108:32:471
5022991610,6cyclictest0-21swapper/011:00:290
5022991610,6cyclictest0-21swapper/009:17:550
5022991610,6cyclictest0-21swapper/009:17:550
5022991610,5cyclictest0-21swapper/009:07:560
5023991513,1cyclictest12395-21ls11:32:481
5023991510,5cyclictest0-21swapper/107:19:291
5023991510,0cyclictest0-21swapper/108:46:211
5023991510,0cyclictest0-21swapper/107:31:001
5022991515,0cyclictest0-21swapper/009:56:030
5022991515,0cyclictest0-21swapper/007:58:570
5022991514,1cyclictest0-21swapper/009:31:400
5022991514,0cyclictest8914-21cat10:02:450
5022991513,1cyclictest0-21swapper/007:07:370
5022991511,3cyclictest81ktimersoftd/008:52:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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