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2021-07-26 - 18:52

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Mon Jul 26, 2021 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2440826856,8sleep10-21swapper/107:06:491
2406926746,17sleep00-21swapper/007:03:190
116952650,0sleep10-21swapper/109:55:081
28312210,1sleep10-21swapper/109:42:181
25582200,0sleep00-21swapper/009:42:130
24593991816,1cyclictest26395-21cat07:11:501
24593991717,0cyclictest0-21swapper/107:58:251
24593991710,1cyclictest91rcu_preempt08:37:111
24593991710,1cyclictest24-21ksoftirqd/109:18:371
24592991716,1cyclictest22804-21smartctl09:27:100
24592991716,1cyclictest20736-21ssh12:24:080
2459399168,2cyclictest1839-21apache_accesses10:27:071
24593991616,0cyclictest0-21swapper/108:07:231
24593991614,1cyclictest1566-21ssh10:26:491
24593991610,6cyclictest24-21ksoftirqd/112:32:171
24593991610,1cyclictest91rcu_preempt09:50:101
24593991610,0cyclictest0-21swapper/109:15:001
24593991610,0cyclictest0-21swapper/108:22:271
24592991616,0cyclictest0-21swapper/011:20:240
24592991615,1cyclictest1485-21ssh10:26:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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