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2023-02-06 - 13:58

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Mon Feb 06, 2023 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286512730,1sleep0596-21lldpd23:33:000
3132626855,8sleep10-21swapper/119:03:361
3139126654,8sleep00-21swapper/019:04:150
269862640,0sleep10-21swapper/120:18:151
20742520,0sleep12073-21ssh23:38:561
231362360,0sleep123138-21ssh23:24:401
31933991816,1cyclictest6644-21ntpq20:48:181
31933991810,0cyclictest0-21swapper/123:33:211
31933991716,0cyclictest7061-21ssh23:46:431
31933991715,1cyclictest27297-21ls00:13:241
31933991710,7cyclictest0-21swapper/122:33:451
31932991716,1cyclictest24421-21ssh21:20:440
31932991710,7cyclictest0-21swapper/020:22:360
31932991710,0cyclictest0-21swapper/022:10:340
248502170,0sleep10-21swapper/122:03:231
31933991615,1cyclictest7622-21ssh00:29:241
31933991614,1cyclictest5329-21ssh23:02:471
31933991614,1cyclictest19233-21ssh00:02:481
31933991610,0cyclictest0-21swapper/100:24:261
31932991616,0cyclictest20485-21ssh22:38:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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