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2024-04-24 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Wed Apr 24, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2066127261,7sleep00-21swapper/019:04:050
2069426957,8sleep10-21swapper/119:04:271
75622630,0sleep00-21swapper/021:13:360
28572620,0sleep10-21swapper/100:16:101
311702200,1sleep00-21swapper/022:35:110
20925991716,1cyclictest26120-21ssh22:26:371
20924991717,0cyclictest0-21swapper/019:25:210
266392160,0sleep10-21swapper/100:03:481
20925991616,0cyclictest23320-21ssh22:23:001
20925991615,1cyclictest28681-21ssh23:18:451
20925991615,1cyclictest24506-21ssh21:37:201
20925991611,2cyclictest12206-21ssh22:06:011
20925991610,6cyclictest0-21swapper/122:41:061
20924991611,4cyclictest21337-21kworker/0:023:41:110
20924991610,6cyclictest0-21swapper/021:00:480
20925991515,0cyclictest0-21swapper/123:36:171
20925991515,0cyclictest0-21swapper/121:29:011
20925991515,0cyclictest0-21swapper/100:28:461
20925991514,1cyclictest2175-21ssh23:26:231
20925991510,5cyclictest0-21swapper/123:21:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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