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2022-10-04 - 09:01

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Tue Oct 04, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
58627448,21sleep10-21swapper/119:04:001
95427149,17sleep00-21swapper/019:04:030
9182190,0sleep10-21swapper/100:13:471
1102121910,8sleep111028-21apache_accesses22:43:591
123622180,1sleep00-21swapper/000:31:400
2560991716,1cyclictest14675-21ls22:48:581
2560991715,1cyclictest5737-21ssh23:27:241
2559991716,0cyclictest21683-21ssh22:59:140
2559991715,1cyclictest6485-21chrt20:41:140
2559991713,4cyclictest0-21swapper/020:56:510
2559991712,5cyclictest0-21swapper/020:03:230
2559991712,5cyclictest0-21swapper/019:20:230
2559991710,7cyclictest0-21swapper/020:17:230
2559991710,7cyclictest0-21swapper/019:10:230
2559991710,0cyclictest0-21swapper/019:17:230
2560991611,4cyclictest27524-21kworker/1:220:29:371
2560991610,6cyclictest0-21swapper/123:00:201
2560991610,6cyclictest0-21swapper/100:03:091
2559991612,4cyclictest0-21swapper/020:36:230
2559991612,4cyclictest0-21swapper/020:24:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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