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2024-07-27 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Sat Jul 27, 2024 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1378427853,21sleep10-21swapper/119:00:061
36192740,0sleep10-21swapper/100:07:501
1382827058,8sleep00-21swapper/019:00:330
129572220,1sleep00-21swapper/000:19:350
82482210,1sleep081ktimersoftd/023:29:250
14361991917,1cyclictest16218-21ls23:39:281
1540921810,7sleep10-21swapper/120:29:371
14361991716,1cyclictest25208-21ssh23:09:061
14361991715,1cyclictest29681-21sh22:30:291
14361991715,1cyclictest25978-21ssh23:52:491
14361991715,1cyclictest210032sleep120:44:301
14361991711,1cyclictest91rcu_preempt21:48:121
14360991715,1cyclictest299192sleep021:05:260
14360991715,1cyclictest109072sleep000:17:330
14361991615,1cyclictest19853-21perl00:29:271
14361991614,1cyclictest24-21ksoftirqd/122:49:151
14361991610,1cyclictest0-21swapper/122:16:411
14360991615,1cyclictest9084-21awk20:14:260
14360991615,1cyclictest11495-21ssh22:06:470
14360991615,1cyclictest0-21swapper/000:05:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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