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2021-01-21 - 02:24

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Wed Jan 20, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123602710,2sleep12434099cyclictest10:10:371
83192680,2sleep02433999cyclictest10:51:120
2393626855,8sleep10-21swapper/107:05:271
2378426855,9sleep00-21swapper/007:03:530
24340992019,1cyclictest0-21swapper/112:31:051
24340992019,1cyclictest0-21swapper/111:51:251
24340992019,1cyclictest0-21swapper/111:28:431
24340992019,1cyclictest0-21swapper/110:07:281
24340992019,1cyclictest0-21swapper/109:28:401
24340992018,1cyclictest0-21swapper/109:54:361
24340991918,1cyclictest0-21swapper/112:23:031
24340991918,1cyclictest0-21swapper/112:18:031
24340991918,1cyclictest0-21swapper/112:15:551
24340991918,1cyclictest0-21swapper/112:09:391
24340991918,1cyclictest0-21swapper/111:54:221
24340991918,1cyclictest0-21swapper/111:47:241
24340991918,1cyclictest0-21swapper/111:39:271
24340991918,1cyclictest0-21swapper/111:24:271
24340991918,1cyclictest0-21swapper/111:21:531
24340991918,1cyclictest0-21swapper/111:16:391
24340991918,1cyclictest0-21swapper/111:09:401
24340991918,1cyclictest0-21swapper/111:03:111
24340991918,1cyclictest0-21swapper/110:57:531
24340991918,1cyclictest0-21swapper/110:55:091
24340991918,1cyclictest0-21swapper/110:52:371
24340991918,1cyclictest0-21swapper/110:40:121
24340991918,1cyclictest0-21swapper/110:35:501
24340991918,1cyclictest0-21swapper/110:28:261
24340991918,1cyclictest0-21swapper/110:24:261
24340991918,1cyclictest0-21swapper/110:17:431
24340991918,1cyclictest0-21swapper/109:58:291
24340991918,1cyclictest0-21swapper/109:48:451
24340991918,1cyclictest0-21swapper/109:38:341
24340991918,1cyclictest0-21swapper/109:33:581
24340991918,1cyclictest0-21swapper/109:24:281
24340991918,1cyclictest0-21swapper/109:19:551
24340991918,1cyclictest0-21swapper/109:14:071
24340991918,1cyclictest0-21swapper/109:06:541
24340991918,1cyclictest0-21swapper/108:59:561
24340991918,1cyclictest0-21swapper/108:47:181
24340991918,0cyclictest626-21diskmemload10:46:291
24340991917,2cyclictest0-21swapper/112:04:551
24340991917,1cyclictest0-21swapper/112:33:051
24340991817,1cyclictest0-21swapper/111:58:331
24340991817,1cyclictest0-21swapper/111:33:061
24340991817,1cyclictest0-21swapper/110:17:541
24340991817,1cyclictest0-21swapper/109:43:031
24340991817,1cyclictest0-21swapper/109:08:161
24340991817,1cyclictest0-21swapper/108:53:181
24340991817,1cyclictest0-21swapper/108:48:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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