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2022-01-26 - 11:58

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Wed Jan 26, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167727159,8sleep00-21swapper/019:01:230
90427057,8sleep10-21swapper/119:00:561
130022490,1sleep00-21swapper/019:31:100
2868991716,1cyclictest5364-21ssh21:31:371
2868991715,1cyclictest14157-21rm21:44:171
2867991716,1cyclictest13563-21ntpq22:26:140
276021710,4sleep091rcu_preempt00:24:390
2868991616,0cyclictest26372-21ssh00:11:291
2868991616,0cyclictest12898-21ssh23:09:461
2868991615,1cyclictest16812-21ssh23:15:061
2868991610,6cyclictest0-21swapper/121:17:121
2868991610,6cyclictest0-21swapper/120:01:171
2868991610,6cyclictest0-21swapper/100:22:081
2868991610,0cyclictest0-21swapper/122:41:031
2867991615,1cyclictest9509-21ssh23:05:250
2868991515,0cyclictest20290-21ssh00:02:481
2868991515,0cyclictest1861-21ssh22:54:551
2868991515,0cyclictest0-21swapper/123:37:411
2868991515,0cyclictest0-21swapper/121:00:431
2868991515,0cyclictest0-21swapper/120:41:161
2868991514,1cyclictest9117-21sshd23:47:391
2868991514,1cyclictest5577-21ssh00:27:261
2868991514,1cyclictest11408-21ssh22:23:471
2868991514,0cyclictest18323-21rm22:32:421
2868991513,1cyclictest1204-21seq20:24:081
2868991512,2cyclictest12098-21apache223:53:361
2868991510,5cyclictest0-21swapper/123:43:221
2868991510,0cyclictest0-21swapper/122:58:161
2868991510,0cyclictest0-21swapper/122:36:531
2868991510,0cyclictest0-21swapper/121:01:101
2868991510,0cyclictest0-21swapper/120:39:161
2868991510,0cyclictest0-21swapper/120:35:161
2868991510,0cyclictest0-21swapper/119:30:271
2868991510,0cyclictest0-21swapper/119:09:241
2867991515,0cyclictest0-21swapper/022:04:270
2867991514,1cyclictest31226-21ssh23:34:180
2867991510,5cyclictest0-21swapper/021:18:110
2867991510,5cyclictest0-21swapper/019:24:250
2867991510,5cyclictest0-21swapper/000:34:080
2867991510,4cyclictest0-21swapper/022:44:590
2867991510,4cyclictest0-21swapper/000:25:550
2867991510,0cyclictest0-21swapper/019:49:280
2867991510,0cyclictest0-21swapper/000:11:550
2868991414,0cyclictest4366-21ssh22:14:521
2868991414,0cyclictest18941-21ssh21:07:021
2868991414,0cyclictest0-21swapper/122:05:561
2868991414,0cyclictest0-21swapper/120:49:481
2868991412,2cyclictest12098-21apache223:23:151
2868991412,1cyclictest99550irq/99-eth0-rx-23:16:091
2868991412,1cyclictest17379-21diskmemload23:59:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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