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2025-03-16 - 23:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Sun Mar 16, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
344027050,8sleep00-21swapper/007:07:050
357126754,9sleep10-21swapper/107:08:271
190122630,0sleep10-21swapper/112:36:351
117082420,0sleep10-21swapper/107:28:551
3772993310,22cyclictest0-21swapper/110:19:431
3772993210,19cyclictest0-21swapper/108:27:581
3772993028,1cyclictest24-21ksoftirqd/110:18:391
3772992927,1cyclictest24-21ksoftirqd/107:33:411
3771992810,8cyclictest0-21swapper/009:14:260
3772992727,0cyclictest0-21swapper/108:12:401
3772992726,0cyclictest24-21ksoftirqd/108:33:591
3771992725,1cyclictest7-21ksoftirqd/011:53:530
377199270,5cyclictest0-21swapper/011:22:200
3772992619,3cyclictest0-21swapper/109:43:481
3772992610,15cyclictest0-21swapper/110:47:441
377199260,24cyclictest0-21swapper/010:21:550
3772992524,0cyclictest24-21ksoftirqd/109:39:381
3772992523,1cyclictest24-21ksoftirqd/111:14:121
3771992516,7cyclictest13622-21apache208:26:050
3771992510,3cyclictest0-21swapper/010:48:550
377299243,16cyclictest2163-21rm12:14:151
3772992419,1cyclictest24-21ksoftirqd/110:07:191
3772992410,14cyclictest0-21swapper/111:41:331
3771992422,0cyclictest0-21swapper/009:04:110
3771992410,2cyclictest0-21swapper/010:39:520
3771992410,10cyclictest0-21swapper/010:47:330
377299234,11cyclictest0-21swapper/108:38:521
3772992322,0cyclictest24-21ksoftirqd/111:34:011
3772992322,0cyclictest24-21ksoftirqd/110:57:001
3772992322,0cyclictest24-21ksoftirqd/109:13:401
3772992320,2cyclictest13848-21perf08:58:391
377299230,3cyclictest91rcu_preempt10:43:081
377299230,12cyclictest0-21swapper/107:58:561
3771992316,6cyclictest13622-21apache210:07:320
3771992310,1cyclictest0-21swapper/012:01:160
377299226,14cyclictest344-21kworker/u4:012:23:281
3772992222,0cyclictest24-21ksoftirqd/112:12:321
3772992220,1cyclictest24-21ksoftirqd/111:03:451
3772992214,5cyclictest0-21swapper/107:14:281
3772992212,3cyclictest97750irq/106-eth1-rx09:54:261
3772992210,6cyclictest0-21swapper/112:27:191
377199226,10cyclictest0-21swapper/008:03:530
3771992222,0cyclictest0-21swapper/010:36:380
3771992217,4cyclictest81ktimersoftd/011:51:170
3771992217,4cyclictest717-21snmpd09:31:030
3771992210,7cyclictest0-21swapper/011:13:500
3771992210,3cyclictest0-21swapper/009:53:490
3771992210,1cyclictest0-21swapper/012:17:510
377199220,1cyclictest0-21swapper/010:01:280
3772992120,1cyclictest24-21ksoftirqd/110:11:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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