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2022-06-27 - 16:38

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Mon Jun 27, 2022 12:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
853721230,0sleep10-21swapper/109:31:241
897026957,8sleep00-21swapper/007:07:160
879226755,8sleep10-21swapper/107:05:261
48802640,0sleep00-21swapper/011:39:180
9349991816,1cyclictest28420-21ls12:10:071
9348991810,7cyclictest0-21swapper/012:20:410
9348991810,7cyclictest0-21swapper/009:29:330
9349991616,0cyclictest7301-21ssh12:25:171
9349991615,1cyclictest30599-21ssh10:00:411
9349991615,1cyclictest25184-21ssh11:22:131
9349991615,1cyclictest16151-21rm09:41:421
9349991615,1cyclictest10787-21ls08:34:361
9349991614,1cyclictest24-21ksoftirqd/107:24:191
9348991616,0cyclictest0-21swapper/007:22:050
9348991615,1cyclictest31755-21ssh10:03:270
9348991615,1cyclictest23851-21ssh09:52:050
9348991615,0cyclictest12454-21ssh09:36:400
9348991614,1cyclictest24559-21ssh11:20:570
9348991610,6cyclictest0-21swapper/007:52:120
9348991610,0cyclictest0-21swapper/011:07:470
9348991610,0cyclictest0-21swapper/008:47:210
396421610,4sleep00-21swapper/010:09:330
9349991515,0cyclictest10776-21sshd07:10:431
9349991515,0cyclictest0-21swapper/111:01:001
9349991514,1cyclictest20480-21ssh10:31:071
9349991514,1cyclictest12620-21ssh10:20:151
9349991513,1cyclictest23968-21taskset10:35:561
9349991513,1cyclictest10634-21users12:29:391
9349991510,5cyclictest0-21swapper/110:51:281
9349991510,5cyclictest0-21swapper/109:14:401
9349991510,4cyclictest0-21swapper/110:56:001
9348991515,0cyclictest0-21swapper/010:44:400
9348991515,0cyclictest0-21swapper/008:42:200
9348991515,0cyclictest0-21swapper/008:19:130
9348991515,0cyclictest0-21swapper/007:37:080
9348991515,0cyclictest0-21swapper/007:29:360
9348991514,1cyclictest30350-21ssh09:17:300
9348991514,0cyclictest27881-21sh10:41:330
9348991510,5cyclictest0-21swapper/012:33:290
9348991510,5cyclictest0-21swapper/009:05:400
9348991510,5cyclictest0-21swapper/009:05:400
9348991510,5cyclictest0-21swapper/007:27:460
9348991510,0cyclictest0-21swapper/008:26:340
934999149,1cyclictest0-21swapper/110:11:081
9349991414,0cyclictest0-21swapper/108:16:271
9349991412,2cyclictest19250-21apache211:54:081
9349991412,2cyclictest19250-21apache211:30:071
9349991412,1cyclictest93750irq/100-eth0-rx10:42:011
9349991412,1cyclictest633-21nscd08:59:351
9349991412,1cyclictest399-21apache207:27:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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