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2023-01-30 - 05:34

x86 Intel Celeron G3900 @2800 MHz, Linux 4.16.15-rt7 (Profile)

Latency plot of system in rack #c, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Mon Jan 30, 2023 00:43:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
511121170,0sleep00-21swapper/022:38:290
1044921150,0sleep10-21swapper/122:45:111
23622750,1sleep10-21swapper/120:03:221
1282127159,8sleep10-21swapper/119:06:361
229732650,0sleep10-21swapper/100:21:021
1279926552,8sleep00-21swapper/019:06:210
270862210,0sleep00-21swapper/019:43:220
13145991816,1cyclictest16740-21ls21:33:261
13143991810,7cyclictest11410-21ssh21:27:530
13145991716,0cyclictest30942-21ssh22:30:391
13145991716,0cyclictest25955-21ssh21:44:281
13145991710,6cyclictest14442-21ssh23:30:271
13143991715,1cyclictest6675-21rm23:20:310
13143991715,1cyclictest21538-21expr00:18:300
13143991710,7cyclictest0-21swapper/019:28:320
13145991616,0cyclictest27385-21ssh21:08:151
13145991616,0cyclictest11713-21ssh23:27:431
13145991616,0cyclictest0-21swapper/121:53:371
13145991615,1cyclictest31475-21ssh00:31:351
13145991615,1cyclictest31475-21ssh00:31:351
13145991615,1cyclictest14762-21ssh21:31:221
13145991614,1cyclictest29800-21ssh23:08:251
13145991611,4cyclictest21812-21kworker/1:023:43:281
13145991610,6cyclictest0-21swapper/123:03:301
13145991610,6cyclictest0-21swapper/122:48:231
13145991610,0cyclictest0-21swapper/122:13:271
13145991610,0cyclictest0-21swapper/121:13:311
13143991616,0cyclictest10026-21ssh22:44:230
13143991615,0cyclictest7126-21ssh00:01:380
13143991615,0cyclictest18793-21ssh00:15:450
13143991614,1cyclictest31602-21ssh23:52:060
13143991610,5cyclictest0-21swapper/021:47:030
13145991515,0cyclictest0-21swapper/122:11:581
13145991515,0cyclictest0-21swapper/100:04:031
13145991514,1cyclictest4478-21ssh22:38:231
13145991514,1cyclictest22744-21ssh23:00:301
13145991514,0cyclictest23626-21ssh21:42:501
13145991514,0cyclictest13503-21ssh00:08:521
13145991512,2cyclictest22304-21apache223:55:371
13145991512,2cyclictest22287-21apache222:57:041
13145991512,2cyclictest22287-21apache221:25:071
13145991510,5cyclictest0-21swapper/123:51:421
13145991510,4cyclictest21812-21kworker/1:019:34:281
13145991510,4cyclictest16854-21kworker/1:100:13:401
13145991510,0cyclictest0-21swapper/120:20:421
13145991510,0cyclictest0-21swapper/120:17:421
13143991514,1cyclictest16358-21df22:53:230
13143991514,0cyclictest27796-21ssh23:47:410
13143991514,0cyclictest24549-21sort23:03:220
13143991511,4cyclictest0-21swapper/020:29:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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