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2022-01-23 - 10:09

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot5.osadl.org (updated Sun Jan 23, 2022 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
90722340,0sleep00-21swapper/021:20:190
2237899300,29cyclictest32214-21meminfo20:55:241
2237899290,28cyclictest4945-21meminfo19:45:221
2237799280,27cyclictest1795-21meminfo21:00:240
2237899270,26cyclictest6458-21meminfo22:35:241
2237899230,22cyclictest7637-21meminfo21:15:241
2237799220,22cyclictest16220-21meminfo23:00:220
2237799220,21cyclictest26385-21meminfo20:40:230
2237899210,21cyclictest15041-21meminfo00:20:231
2237899210,20cyclictest992-21meminfo19:35:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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