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2023-02-07 - 19:00

x86 Intel Celeron G3900 @2800 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot5.osadl.org (updated Tue Feb 07, 2023 12:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1513899290,28cyclictest4635-21meminfo09:25:270
1513899290,28cyclictest10483-21meminfo09:40:210
1513999260,25cyclictest31154-21meminfo09:10:241
1513999250,24cyclictest24917-21meminfo11:40:221
1513899240,23cyclictest32714-21meminfo12:00:220
1513999230,22cyclictest13967-21meminfo12:35:201
1513999230,22cyclictest12027-21meminfo12:30:231
1513899230,22cyclictest28185-21meminfo07:40:200
1513999220,21cyclictest26224-21meminfo07:35:221
1513899220,21cyclictest30130-21meminfo07:45:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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