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2021-10-24 - 02:12

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot5.osadl.org (updated Fri Oct 15, 2021 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252872580,1sleep02321-21runrttasks12:24:100
3169399290,28cyclictest9265-21meminfo08:55:191
3169299260,25cyclictest29397-21meminfo11:10:200
3169399250,24cyclictest22296-21meminfo12:15:181
3169399230,22cyclictest31339-21meminfo11:15:211
3169299230,23cyclictest20357-21meminfo12:10:210
3169299230,23cyclictest20283-21meminfo08:00:210
3169399220,22cyclictest14516-21meminfo11:55:161
3169299220,21cyclictest18432-21meminfo12:05:270
3169399210,21cyclictest18147-21meminfo07:55:201
3169399210,20cyclictest28732-21meminfo09:45:261
3169399200,20cyclictest871-21meminfo11:20:171
3169399200,19cyclictest32379-21meminfo07:10:251
31692992018,1cyclictest11-21ksoftirqd/009:10:220
31693991917,1cyclictest8464-21awk08:55:001
3169399190,18cyclictest29396-21meminfo11:10:201
3169399190,18cyclictest15803-21meminfo10:35:301
3169299190,18cyclictest20948-21meminfo09:25:220
3169399180,17cyclictest26093-21meminfo08:15:191
31693991715,1cyclictest2253-21tail07:15:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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