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2023-06-08 - 07:29

x86 Intel Celeron G3900 @2800 MHz, Linux 6.1.12-rt7 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot5.osadl.org (updated Thu Jun 08, 2023 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18532770,1sleep01852-21seq22:06:260
214982680,1sleep021497-21seq23:00:220
3212099470,45cyclictest26890-21meminfo20:20:251
3211999420,40cyclictest2763-21meminfo19:15:240
3212099410,39cyclictest9522-21meminfo23:55:291
3211999410,40cyclictest11203-21meminfo21:05:250
3211999410,39cyclictest29750-21meminfo21:55:300
3212099400,38cyclictest22329-21meminfo21:35:271
3211999400,39cyclictest2099-21meminfo23:35:250
3211999400,39cyclictest17608-21meminfo19:55:280
3211999400,38cyclictest12209-21meminfo22:35:230
3212099390,38cyclictest7490-21meminfo20:55:281
3212099390,38cyclictest27047-21meminfo23:15:261
3212099390,37cyclictest10361-21meminfo22:30:251
3211999390,38cyclictest23347-21meminfo23:05:240
3211999390,37cyclictest5633-21meminfo20:50:240
3211999380,37cyclictest9523-21meminfo23:55:280
3211999380,36cyclictest8515-21meminfo22:25:270
3211999380,36cyclictest3966-21meminfo23:40:240
3211999380,36cyclictest21318-21meminfo20:05:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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