You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-02-06 - 14:13

x86 Intel Celeron G3900 @2800 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot5.osadl.org (updated Mon Feb 06, 2023 00:43:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40399280,28cyclictest25518-21meminfo00:20:201
40299280,27cyclictest21619-21meminfo00:10:290
40399270,26cyclictest30601-21meminfo23:10:181
40299270,26cyclictest1328-21meminfo21:55:190
40399240,24cyclictest22041-21meminfo21:25:201
40399240,23cyclictest19657-21meminfo00:05:181
40299240,23cyclictest25168-21meminfo20:10:170
40299240,23cyclictest15758-21meminfo23:55:180
40399230,22cyclictest3736-21meminfo19:15:241
40399230,22cyclictest17729-21meminfo00:00:241
40299230,22cyclictest23984-21meminfo21:30:170
40299230,22cyclictest23227-21meminfo20:05:190
40299220,22cyclictest4074-21meminfo23:25:160
40299220,21cyclictest8383-21meminfo20:50:170
40299220,21cyclictest20866-21meminfo22:45:170
40299210,21cyclictest19318-21meminfo19:55:170
40299210,20cyclictest6020-21meminfo23:30:190
40299210,20cyclictest27114-21meminfo20:15:180
40399200,19cyclictest7205-21meminfo22:10:181
40399200,19cyclictest18129-21meminfo21:15:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional