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2021-07-26 - 19:07

Intel(R) Celeron(R) CPU G3900 @ 2.80GHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot5.osadl.org (updated Mon Jul 26, 2021 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2438699270,26cyclictest8508-21meminfo10:35:261
2438699270,26cyclictest3065-21meminfo07:35:211
2438699270,26cyclictest18810-21meminfo08:15:231
2438599250,24cyclictest29887-21meminfo11:30:160
2438599250,24cyclictest25066-21meminfo07:10:200
2438599220,22cyclictest11726-21meminfo09:20:240
2438699210,21cyclictest11143-21meminfo12:05:281
2438699210,20cyclictest3352-21meminfo11:45:211
2438699210,20cyclictest10840-21meminfo07:55:211
2438599210,20cyclictest14936-21meminfo08:05:250
2438699190,19cyclictest1389-21meminfo11:40:211
2438699190,18cyclictest29579-21meminfo07:20:201
2438699180,18cyclictest27287-21meminfo10:00:261
2438599180,18cyclictest22720-21meminfo08:25:320
2438599180,17cyclictest1043-21meminfo07:30:200
2438699170,17cyclictest654-21meminfo10:15:191
2438699170,17cyclictest32419-21meminfo08:50:211
24385991711,2cyclictest2321-21runrttasks08:48:100
2438599170,10cyclictest2533-21/usr/sbin/munin08:55:340
2438699160,15cyclictest12952-21meminfo08:00:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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