You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-10-04 - 09:14

x86 Intel Celeron G3900 @2800 MHz, Linux 5.10.35-rt39 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot5.osadl.org (updated Tue Oct 04, 2022 00:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1929799300,29cyclictest19996-21meminfo21:55:191
1929699270,26cyclictest12213-21meminfo21:35:180
1929699260,25cyclictest12909-21meminfo23:00:180
1929799250,24cyclictest30409-21meminfo23:45:201
1929799250,24cyclictest13593-21meminfo00:25:201
1929699250,24cyclictest23899-21meminfo22:05:210
1929699250,24cyclictest10282-21meminfo21:30:240
1929699240,23cyclictest18734-21meminfo23:15:230
1929699210,14cyclictest2375-21awk22:35:000
1929799190,19cyclictest4431-21meminfo21:15:211
1929799190,19cyclictest25845-21meminfo22:10:251
1929799190,18cyclictest20700-21meminfo23:20:181
1929699190,19cyclictest16109-21meminfo21:45:200
1929799180,17cyclictest6396-21meminfo21:20:221
1929799180,17cyclictest19973-21meminfo19:10:181
1929799175,8cyclictest7652-21ls20:00:241
1929799170,17cyclictest18048-21meminfo21:50:181
1929799170,16cyclictest5810-21meminfo00:05:181
1929799170,16cyclictest15530-21meminfo00:30:191
1929799170,16cyclictest15436-21meminfo20:20:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional