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2023-06-05 - 21:59

x86 Intel Celeron G3900 @2800 MHz, Linux 6.1.12-rt7 (Profile)

Latency plot of system in rack #c, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot5.osadl.org (updated Mon Jun 05, 2023 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51892660,0sleep00-21swapper/010:20:280
3010599490,47cyclictest21608-21meminfo11:05:360
3010699480,46cyclictest29012-21meminfo11:25:281
3010599480,46cyclictest4052-21meminfo11:45:240
3010599480,46cyclictest32718-21meminfo11:35:270
3010699470,45cyclictest3028-21meminfo10:15:281
3010699430,41cyclictest11474-21meminfo12:05:251
3010599420,40cyclictest3869-21meminfo08:50:230
3010599410,39cyclictest17044-21meminfo12:20:250
3010699400,39cyclictest4899-21meminfo10:20:251
3010699400,39cyclictest27978-21meminfo09:55:241
3010599400,39cyclictest17866-21meminfo10:55:230
3010699390,38cyclictest26979-21meminfo08:25:281
3010699390,38cyclictest10445-21meminfo10:35:211
3010699390,37cyclictest3871-21meminfo08:50:241
3010699390,37cyclictest22428-21meminfo09:40:211
3010699380,37cyclictest14163-21meminfo10:45:211
3010699380,36cyclictest6323-21meminfo07:30:231
3010699380,36cyclictest22592-21meminfo12:35:231
3010599380,37cyclictest7750-21meminfo11:55:240
3010599380,36cyclictest30861-21meminfo11:30:250
3010699370,36cyclictest26126-21meminfo09:50:221
3010699370,36cyclictest15028-21meminfo09:20:351
3010699370,35cyclictest11300-21meminfo09:10:281
3010599370,36cyclictest30704-21meminfo07:10:260
3010599370,35cyclictest5722-21meminfo08:55:280
3010699360,35cyclictest15171-21meminfo12:15:261
3010699360,34cyclictest32521-21meminfo07:15:011
3010699360,34cyclictest17867-21meminfo10:55:241
3010699360,34cyclictest1147-21meminfo10:10:301
3010599360,35cyclictest23261-21meminfo08:15:300
3010599360,35cyclictest21408-21meminfo08:10:260
3010599360,35cyclictest17706-21meminfo08:00:260
3010699350,34cyclictest10085-21meminfo07:40:221
3010699350,33cyclictest11936-21meminfo07:45:261
3010699340,33cyclictest20742-21meminfo12:30:251
3010599340,33cyclictest9619-21meminfo12:00:230
3010599340,33cyclictest27159-21meminfo11:20:260
3010599340,33cyclictest16022-21meminfo10:50:270
3010599340,33cyclictest12328-21meminfo10:40:310
3010699320,31cyclictest23436-21meminfo11:10:231
3010699320,30cyclictest2016-21meminfo08:45:221
3010699310,29cyclictest7584-21meminfo09:00:231
3010699310,29cyclictest2202-21meminfo11:40:251
3010599300,29cyclictest3029-21meminfo10:15:280
3010699290,28cyclictest4478-21meminfo07:25:281
3010699290,28cyclictest32547-21meminfo08:40:241
3010699290,27cyclictest31703-21meminfo10:05:241
3010699290,27cyclictest29844-21meminfo10:00:241
3010599290,28cyclictest13319-21meminfo12:10:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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