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2024-10-13 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot5.osadl.org (updated Sun Oct 13, 2024 13:05:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5515:03:316482
51,15:02:366481
015:02:366477
0,15:02:366476
0,15:02:366475
0,15:02:366474
0,15:02:366473
0,15:02:366472
0,15:02:366471
0,15:02:366470
0,15:02:366469
0,15:02:366468
0,15:02:366467
0,15:02:366466
0,15:02:366465
0,15:02:366464
0,15:02:366463
0,15:02:366462
0,15:02:366461
0,15:02:366460
0,15:02:366459
0,15:02:366458
0,15:02:366457
0,15:02:366456
0,15:02:366455
0,15:02:366454
0,15:02:366453
0,15:02:366452
0,15:02:366451
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0,15:02:366449
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0,15:02:366447
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0,15:02:366444
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0,15:02:366440
0,15:02:366439
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0,15:02:366437
0,15:02:366436
0,15:02:366435
0,15:02:366434
0,15:02:366433
0,15:02:366432
0,15:02:366431
0,15:02:366430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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