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2023-11-28 - 20:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot5.osadl.org (updated Tue Nov 28, 2023 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1200599586,50cyclictest30679-21meminfo22:55:271
1200599500,48cyclictest28023-21meminfo19:50:261
1200499500,48cyclictest26149-21meminfo00:10:340
1200499500,48cyclictest1173-21meminfo20:05:270
1200599490,47cyclictest17906-21meminfo20:50:271
1200499480,46cyclictest8632-21meminfo20:25:260
1200499470,45cyclictest27984-21meminfo00:15:280
1200499470,45cyclictest10276-21meminfo22:00:280
1200599460,44cyclictest3868-21meminfo23:10:291
1200499440,42cyclictest12339-21meminfo20:35:300
1200499430,41cyclictest26174-21meminfo19:45:260
1200599420,40cyclictest8630-21meminfo20:25:251
1200499420,40cyclictest15031-21meminfo19:15:250
1200499420,40cyclictest10477-21meminfo20:30:250
1200599410,39cyclictest4910-21meminfo20:15:271
1200499410,40cyclictest20603-21meminfo19:30:250
1200499410,39cyclictest6785-21meminfo20:20:300
1200499410,39cyclictest31704-21meminfo00:25:260
1200499410,39cyclictest18709-21meminfo23:50:250
1200599400,38cyclictest31738-21meminfo20:00:251
1200599390,37cyclictest27177-21meminfo21:15:261
1200499390,37cyclictest16866-21meminfo23:45:290
1200499380,37cyclictest3039-21meminfo00:35:280
1200499380,37cyclictest23478-21meminfo21:05:290
1200599370,35cyclictest16057-21meminfo20:45:261
1200599360,35cyclictest6552-21meminfo21:50:251
1200499360,35cyclictest23254-21meminfo22:35:270
1200499360,34cyclictest29052-21meminfo21:20:270
1200499350,33cyclictest32540-21meminfo23:00:250
1200499350,33cyclictest11286-21meminfo23:30:280
1200599340,33cyclictest21405-21meminfo22:30:281
1200599340,32cyclictest9439-21meminfo23:25:281
1200599340,32cyclictest12607-21meminfo19:10:261
1200499340,33cyclictest2846-21meminfo21:40:180
1200499340,32cyclictest16056-21meminfo20:45:260
1200599330,31cyclictest20562-21meminfo23:55:261
1200599330,31cyclictest14117-21meminfo19:15:021
1200499330,31cyclictest24327-21meminfo19:40:260
1200599320,31cyclictest26975-21meminfo22:45:261
1200499320,31cyclictest27178-21meminfo21:15:260
1200499320,30cyclictest29856-21meminfo00:20:290
1200599310,30cyclictest30898-21meminfo21:25:261
1200599310,30cyclictest2019-21meminfo23:05:291
1200499310,30cyclictest24281-21meminfo00:05:270
1200499310,30cyclictest12127-21meminfo22:05:260
1200499310,29cyclictest7584-21meminfo23:20:270
1200499310,29cyclictest25330-21meminfo21:10:250
1200499310,29cyclictest22458-21meminfo19:35:270
1200499310,29cyclictest21621-21meminfo21:00:230
1200499300,29cyclictest29873-21meminfo19:55:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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