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2024-07-13 - 08:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jul 13, 2024 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3954209910012,51cyclictest713332-21df00:35:115
5083342960,0sleep10-21swapper/121:43:001
39518229354,12sleep70-21swapper/719:09:527
39519129256,12sleep50-21swapper/519:09:575
39509929155,12sleep20-21swapper/219:08:412
395435998616,37cyclictest0-21swapper/719:10:127
395420998414,38cyclictest0-21swapper/520:45:115
395412998415,38cyclictest0-21swapper/419:25:114
395420998315,34cyclictest0-21swapper/521:50:115
395412998316,37cyclictest0-21swapper/423:15:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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