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2026-05-18 - 11:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon May 18, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3730888993811,379cyclictest0-21swapper/419:27:024
3730888993810,380cyclictest0-21swapper/420:32:024
3730888993810,380cyclictest0-21swapper/420:32:014
3730888993810,380cyclictest0-21swapper/419:12:014
3730888993800,379cyclictest0-21swapper/420:12:024
3730888993800,1cyclictest0-21swapper/419:47:024
3730888993800,1cyclictest0-21swapper/419:43:024
373087499380379,1cyclictest3770787-21kworker/2:023:17:022
373087499379378,1cyclictest3770787-21kworker/2:000:16:022
373087499378376,1cyclictest3770787-21kworker/2:022:39:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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