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2024-04-24 - 04:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Apr 23, 2024 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2737602136118,16sleep20-21swapper/219:05:112
27588329957,11sleep10-21swapper/119:08:321
27401229980,17sleep30-21swapper/319:05:133
276173999728,37cyclictest0-21swapper/020:53:170
27422229576,3sleep50-21swapper/519:05:145
276213998614,39cyclictest0-21swapper/523:23:165
3875392840,0sleep00-21swapper/021:43:530
3875392840,0sleep00-21swapper/021:43:530
27582928360,11sleep40-21swapper/419:07:474
276220998215,36cyclictest0-21swapper/600:08:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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