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2024-04-16 - 03:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Mon Apr 15, 2024 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278893329457,11sleep70-21swapper/719:07:587
278893329457,11sleep70-21swapper/719:07:587
278701929374,17sleep60-21swapper/619:05:076
278701929374,17sleep60-21swapper/619:05:076
30759652910,0sleep1201rcuc/100:09:571
278816229172,17sleep00-21swapper/019:05:170
278816229172,17sleep00-21swapper/019:05:170
2789278998817,40cyclictest0-21swapper/319:53:153
28106342860,0sleep70-21swapper/719:45:067
30027632850,1sleep03002760-21sh23:08:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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