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2025-03-25 - 22:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Tue Mar 25, 2025 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260935699386382,3cyclictest2643245-21kworker/4:011:46:014
260935699385381,3cyclictest2643245-21kworker/4:011:36:014
260935699385381,3cyclictest2643245-21kworker/4:011:36:014
260935699384380,3cyclictest2760410-21kworker/4:212:06:024
260935699384380,3cyclictest2616031-21kworker/4:107:32:024
260935699383380,3cyclictest2643245-21kworker/4:009:46:014
2609356993810,380cyclictest0-21swapper/411:25:024
2609356993810,380cyclictest0-21swapper/409:28:024
260935699380379,1cyclictest1625116-21kworker/4:207:15:034
260935699380379,1cyclictest1625116-21kworker/4:207:15:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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