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2025-07-10 - 06:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Thu Jul 10, 2025 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
357179993810,380cyclictest0-21swapper/720:29:027
357179993810,380cyclictest0-21swapper/719:56:037
357179993810,1cyclictest0-21swapper/719:51:027
357179993800,379cyclictest0-21swapper/720:50:037
357179993800,1cyclictest0-21swapper/720:47:027
35715099353352,1cyclictest0-21swapper/322:14:023
35713099347346,1cyclictest0-21swapper/122:29:031
35713099343341,1cyclictest500760-21kworker/1:123:05:021
35713099340338,1cyclictest0-21swapper/123:40:021
35713099340338,1cyclictest0-21swapper/122:47:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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