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2025-07-12 - 10:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot6.osadl.org (updated Sat Jul 12, 2025 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
115507799381380,1cyclictest1164887-21kworker/6:020:00:036
1155062993810,380cyclictest0-21swapper/422:02:024
1155062993810,380cyclictest0-21swapper/421:08:014
115507799380379,1cyclictest1164887-21kworker/6:019:57:026
115507799380379,1cyclictest1148893-21kworker/6:220:53:026
115507799380379,1cyclictest1148893-21kworker/6:219:30:036
115507799380379,1cyclictest1148893-21kworker/6:219:16:026
115507799380379,1cyclictest1148893-21kworker/6:219:12:026
115506299380378,1cyclictest1456460-21kworker/4:020:51:024
1155062993800,1cyclictest0-21swapper/421:11:024
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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