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2024-04-14 - 19:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Sun Apr 14, 2024 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26437812137118,3sleep20-21swapper/219:05:192
26429102136117,4sleep30-21swapper/319:05:123
269190821040,1sleep010-21ksoftirqd/020:30:000
2645172999315,38cyclictest0-21swapper/700:23:167
264478029356,11sleep40-21swapper/419:07:544
29227992910,0sleep30-21swapper/300:00:133
26959992860,0sleep70-21swapper/720:35:127
26703562860,0sleep442-21ksoftirqd/419:50:154
264480128259,11sleep70-21swapper/719:08:137
2645172998114,35cyclictest0-21swapper/721:13:167
264480028158,11sleep60-21swapper/619:08:126
264467627956,11sleep50-21swapper/519:06:275
264470027861,11sleep10-21swapper/119:06:471
2645151997726,32cyclictest0-21swapper/421:23:164
2645151997715,35cyclictest0-21swapper/421:58:164
2645151997616,34cyclictest0-21swapper/420:23:164
2645151997615,35cyclictest0-21swapper/420:13:164
2645151997515,35cyclictest0-21swapper/423:33:164
2645151997515,34cyclictest0-21swapper/400:08:164
264207327558,11sleep00-21swapper/019:05:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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