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2024-10-04 - 01:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Thu Oct 03, 2024 00:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4116951993820,381cyclictest0-21swapper/722:49:027
4116951993820,1cyclictest0-21swapper/700:29:027
411695199381380,1cyclictest67653-21kworker/7:023:55:027
411695199381380,1cyclictest67653-21kworker/7:023:11:027
411695199381379,1cyclictest0-21swapper/720:08:027
4116951993810,380cyclictest0-21swapper/722:23:037
4116951993810,380cyclictest0-21swapper/721:42:027
4116951993810,380cyclictest0-21swapper/720:33:027
4116951993810,380cyclictest0-21swapper/700:34:037
411695199380379,1cyclictest67653-21kworker/7:023:28:037
411695199380379,1cyclictest67653-21kworker/7:022:15:027
411695199380378,1cyclictest0-21swapper/722:30:027
4116951993800,379cyclictest0-21swapper/723:30:037
4116951993800,379cyclictest0-21swapper/700:37:037
4116951993800,1cyclictest0-21swapper/721:54:037
4116951993800,1cyclictest0-21swapper/721:23:027
411695199379378,1cyclictest67653-21kworker/7:022:56:037
411695199379378,1cyclictest67653-21kworker/7:022:37:037
411695199379378,1cyclictest4186533-21kworker/7:221:56:027
411695199379378,1cyclictest4186533-21kworker/7:221:45:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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