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2024-07-12 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot6.osadl.org (updated Fri Jul 12, 2024 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11389622090,5sleep763-21ksoftirqd/719:05:117
115679210056,12sleep50-21swapper/519:07:035
11469429981,16sleep00-21swapper/019:05:210
1363792960,0sleep70-21swapper/719:40:297
211099930,80rtkit-daemon0-21swapper/419:08:104
116078999118,38cyclictest0-21swapper/123:35:111
116071999118,40cyclictest0-21swapper/022:15:110
116078998915,37cyclictest0-21swapper/119:55:111
116078998915,37cyclictest0-21swapper/119:55:111
11513428970,3sleep10-21swapper/119:05:301
116071998818,38cyclictest0-21swapper/019:45:110
116119998715,39cyclictest0-21swapper/621:05:116
116078998716,36cyclictest0-21swapper/120:20:111
116071998716,38cyclictest0-21swapper/022:25:120
116119998517,37cyclictest0-21swapper/621:25:116
116119998517,37cyclictest0-21swapper/621:25:116
116119998515,35cyclictest0-21swapper/622:00:116
116071998516,38cyclictest0-21swapper/000:30:110
116119998416,36cyclictest0-21swapper/620:05:116
116078998116,35cyclictest0-21swapper/123:00:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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