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2024-07-27 - 03:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Fri Jul 26, 2024 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
352391021050,1sleep442-21ksoftirqd/422:40:174
363650421020,0sleep30-21swapper/300:15:013
334385229256,11sleep10-21swapper/119:05:311
334386329172,18sleep30-21swapper/319:05:413
334391229056,11sleep50-21swapper/519:06:245
3344381998716,38cyclictest0-21swapper/421:10:134
3344397998316,37cyclictest0-21swapper/622:40:146
3344381998316,36cyclictest0-21swapper/421:20:134
334402028359,12sleep60-21swapper/619:07:536
334389628264,12sleep00-21swapper/019:06:100
334413828154,21sleep20-21swapper/219:09:352
35455162800,1sleep442-21ksoftirqd/422:59:164
211099790,65rtkit-daemon0-21swapper/419:07:014
35986142780,2sleep549-21ksoftirqd/523:42:425
36291092770,0sleep30-21swapper/300:08:043
334391427761,11sleep70-21swapper/719:06:267
33843812750,0sleep70-21swapper/720:15:237
3344357997016,37cyclictest0-21swapper/120:10:141
3344357997012,50cyclictest21-21ksoftirqd/119:25:141
3344357996919,39cyclictest0-21swapper/123:35:131
3344357996917,40cyclictest0-21swapper/100:25:131
3344357996718,39cyclictest0-21swapper/119:15:131
334438199665,28cyclictest0-21swapper/421:30:144
3344357996616,36cyclictest0-21swapper/123:25:141
3344357996417,39cyclictest0-21swapper/120:35:141
3344357994715,7cyclictest121rcu_preempt22:10:131
3344381994110,16cyclictest3624949-21/usr/sbin/munin00:05:134
334437499391,9cyclictest0-21swapper/320:20:143
3344389993617,19cyclictest0-21swapper/522:50:135
3344389993514,21cyclictest0-21swapper/521:40:145
3344389993414,13cyclictest0-21swapper/519:50:145
3344389993414,13cyclictest0-21swapper/519:50:135
3344357993115,15cyclictest0-21swapper/121:15:131
3344389993014,15cyclictest0-21swapper/520:50:135
3344367993014,15cyclictest0-21swapper/223:20:132
3344397992913,15cyclictest0-21swapper/620:25:146
3344381992914,15cyclictest0-21swapper/420:30:144
3344349992928,1cyclictest0-21swapper/019:35:140
35185312280,1sleep656-21ksoftirqd/622:35:226
34071022280,2sleep010-21ksoftirqd/020:55:190
334438999285,12cyclictest0-21swapper/519:10:145
3344381992812,15cyclictest0-21swapper/421:50:134
3344381992812,15cyclictest0-21swapper/419:30:134
3344367992812,15cyclictest0-21swapper/220:15:142
3344397992711,15cyclictest0-21swapper/620:05:146
3344397992711,15cyclictest0-21swapper/600:20:136
3344389992711,15cyclictest0-21swapper/522:35:145
3344381992711,15cyclictest0-21swapper/423:30:134
3344367992711,15cyclictest0-21swapper/221:45:132
3344357992711,15cyclictest0-21swapper/119:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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