You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2022-06-27 - 16:56

x86 Intel Core i7-3770K @3500 MHz, Linux 5.4.102-rt53 (Profile)

Latency plot of system in rack #c, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Mon Jun 27, 2022 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
281373123240,15sleep30-21swapper/319:05:103
281373123240,15sleep30-21swapper/319:05:103
2815645210687,4sleep70-21swapper/719:07:017
2815645210687,4sleep70-21swapper/719:07:007
281579329455,11sleep40-21swapper/419:09:064
281579329455,11sleep40-21swapper/419:09:064
281582929155,11sleep20-21swapper/219:09:372
281582929155,11sleep20-21swapper/219:09:372
281567528956,11sleep00-21swapper/019:07:250
281567528956,11sleep00-21swapper/019:07:250
28950712850,2sleep121-21ksoftirqd/121:20:061
281583328567,12sleep60-21swapper/619:09:406
281583328567,12sleep60-21swapper/619:09:406
2816081998214,37cyclictest0-21swapper/520:41:275
2816081998214,37cyclictest0-21swapper/520:41:265
2816081998214,37cyclictest0-21swapper/500:36:265
2816081998115,35cyclictest0-21swapper/520:16:265
30758312800,0sleep00-21swapper/000:00:180
2816081997915,35cyclictest0-21swapper/521:36:265
29924942780,0sleep20-21swapper/222:45:222
281585027854,12sleep50-21swapper/519:09:575
281585027854,12sleep50-21swapper/519:09:575
281570527760,12sleep10-21swapper/119:07:511
281570527760,12sleep10-21swapper/119:07:511
30593242760,0sleep60-21swapper/623:45:186
30958382740,1sleep763-21ksoftirqd/700:18:527
31094542730,1sleep335-21ksoftirqd/300:30:163
29525632710,2sleep442-21ksoftirqd/422:10:174
29525632710,2sleep442-21ksoftirqd/422:10:164
2816081997015,37cyclictest0-21swapper/519:16:265
31145972670,0sleep30-21swapper/300:35:133
2816061994717,30cyclictest0-21swapper/223:46:262
2816089993130,1cyclictest0-21swapper/623:36:266
2816089993014,16cyclictest0-21swapper/622:26:266
2816089993014,15cyclictest0-21swapper/621:51:266
2816089993014,15cyclictest0-21swapper/621:31:276
2816081993014,15cyclictest0-21swapper/521:56:275
2816074993014,15cyclictest0-21swapper/422:06:274
29262392290,1sleep335-21ksoftirqd/321:46:453
2816089992914,15cyclictest0-21swapper/623:26:276
2816074992913,15cyclictest0-21swapper/419:21:264
2816041992913,15cyclictest0-21swapper/019:11:270
2816089992815,13cyclictest0-21swapper/622:11:266
2816089992815,13cyclictest0-21swapper/622:11:266
2816089992811,17cyclictest2883404-21diskmemload22:51:266
2816081992812,15cyclictest0-21swapper/500:16:265
2816061992812,15cyclictest0-21swapper/219:41:262
2816049992812,15cyclictest0-21swapper/123:31:271
2816061992711,15cyclictest0-21swapper/220:36:262
2816089992622,4cyclictest0-21swapper/600:01:266
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional