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2021-01-17 - 22:39

Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz, Linux 5.10.4-rt21 (Profile)

Latency plot of system in rack #c, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Fri Jan 15, 2021 00:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251126728768,3sleep70-21swapper/719:05:067
251286727138,11sleep30-21swapper/319:07:353
251302026838,10sleep50-21swapper/519:09:465
251300826841,10sleep20-21swapper/219:09:352
251278925945,10sleep00-21swapper/019:06:280
251278625844,10sleep60-21swapper/619:06:276
251270625843,10sleep40-21swapper/419:05:194
251275025638,14sleep10-21swapper/119:05:571
251322799558,25cyclictest0-21swapper/420:17:014
251322799538,25cyclictest0-21swapper/419:41:584
25664932380,0sleep40-21swapper/420:50:084
251321299148,3cyclictest0-21swapper/000:20:400
2513232991312,1cyclictest2519062-21users19:15:176
251322299130,0cyclictest0-21swapper/300:01:313
251321999130,1cyclictest0-21swapper/200:02:352
2513217991312,1cyclictest0-21swapper/122:28:121
251321799130,11cyclictest0-21swapper/119:32:351
251321299131,11cyclictest0-21swapper/022:57:070
25516922120,0sleep437-21ksoftirqd/420:20:054
2513237991212,0cyclictest0-21swapper/723:06:597
2513237991212,0cyclictest0-21swapper/722:49:167
251323799120,12cyclictest0-21swapper/722:22:557
251323799120,12cyclictest0-21swapper/722:07:297
251323799120,12cyclictest0-21swapper/721:51:327
251323799120,12cyclictest0-21swapper/721:44:247
251323799120,12cyclictest0-21swapper/700:11:337
251323799120,0cyclictest0-21swapper/722:16:357
2513232991211,1cyclictest0-21swapper/600:21:276
251323299120,12cyclictest0-21swapper/623:03:536
251323299120,12cyclictest0-21swapper/622:04:146
251323299120,12cyclictest0-21swapper/600:31:326
251323299120,0cyclictest0-21swapper/621:23:536
251323299120,0cyclictest0-21swapper/621:23:536
251322999120,12cyclictest0-21swapper/523:20:595
251322999120,12cyclictest0-21swapper/522:05:035
251322999120,12cyclictest0-21swapper/521:15:175
251322999120,12cyclictest0-21swapper/500:33:015
2513227991212,0cyclictest0-21swapper/422:03:374
251322799120,12cyclictest0-21swapper/400:22:394
251322799120,0cyclictest0-21swapper/423:31:554
2513222991212,0cyclictest0-21swapper/321:55:103
251322299120,12cyclictest0-21swapper/322:39:153
251322299120,12cyclictest0-21swapper/300:12:063
2513219991212,0cyclictest0-21swapper/222:31:512
251321999120,0cyclictest0-21swapper/223:46:002
251321999120,0cyclictest0-21swapper/221:38:502
2513217991211,1cyclictest0-21swapper/123:45:271
251321799120,0cyclictest0-21swapper/122:58:271
251321299120,12cyclictest0-21swapper/023:49:390
251321299120,12cyclictest0-21swapper/021:14:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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