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2023-06-04 - 05:57

x86 Intel Core i7-3770K @3500 MHz, Linux 5.4.102-rt53 (Profile)

Latency plot of system in rack #c, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h200 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot6.osadl.org (updated Sun Jun 04, 2023 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32769632142118,17sleep30-21swapper/319:05:363
3277245210991,17sleep70-21swapper/719:07:497
35437572980,2sleep763-21ksoftirqd/700:02:337
3277641999128,35cyclictest0-21swapper/520:27:275
33756852880,0sleep50-21swapper/521:35:015
3277641998823,36cyclictest0-21swapper/523:17:275
3277648998516,37cyclictest0-21swapper/621:27:276
3277641998216,37cyclictest0-21swapper/523:07:285
3277641998115,37cyclictest0-21swapper/520:02:285
3277641998016,35cyclictest0-21swapper/522:32:285
3277641998015,36cyclictest0-21swapper/522:57:285
327722928057,12sleep20-21swapper/219:07:352
327712728056,12sleep50-21swapper/519:06:105
327709928057,11sleep40-21swapper/419:05:454
327738127962,12sleep00-21swapper/019:09:430
327721527862,11sleep60-21swapper/619:07:236
327721927760,12sleep10-21swapper/119:07:271
35156162750,1sleep4411rcuc/423:37:464
34625202750,0sleep442-21ksoftirqd/422:50:284
33991552750,0sleep60-21swapper/621:55:206
34431522740,0sleep70-21swapper/722:34:307
3277627997415,36cyclictest0-21swapper/323:52:273
3277627997415,35cyclictest0-21swapper/320:52:283
34825172730,0sleep70-21swapper/723:09:067
3277641997110,30cyclictest0-21swapper/520:17:285
3277641997016,36cyclictest0-21swapper/519:42:285
3277641997015,34cyclictest0-21swapper/521:57:285
3277635997014,38cyclictest0-21swapper/421:12:284
3277635997014,38cyclictest0-21swapper/421:12:274
3277641996915,34cyclictest0-21swapper/521:47:285
3277635996915,35cyclictest0-21swapper/421:37:274
3277635996515,38cyclictest0-21swapper/419:32:274
33489322600,0sleep70-21swapper/721:10:207
33489322600,0sleep70-21swapper/721:10:197
3277648996016,34cyclictest0-21swapper/622:22:276
3277648995518,34cyclictest0-21swapper/622:12:276
3277648995515,36cyclictest0-21swapper/622:47:276
3277604993916,23cyclictest0-21swapper/000:07:280
3277604993916,23cyclictest0-21swapper/000:07:270
3277604993815,23cyclictest0-21swapper/020:37:280
3277604993814,24cyclictest0-21swapper/021:02:270
3277656993115,16cyclictest0-21swapper/723:32:277
3277656993114,16cyclictest0-21swapper/722:17:287
34949842300,0sleep50-21swapper/523:20:175
3277627993014,15cyclictest0-21swapper/320:12:273
3277604993014,15cyclictest0-21swapper/023:57:280
3277656992913,15cyclictest0-21swapper/722:02:277
3277656992913,15cyclictest0-21swapper/719:37:287
3277627992813,15cyclictest0-21swapper/323:27:273
34462892270,1sleep43446290-21grep22:35:404
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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