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2025-07-05 - 21:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Sat Jul 05, 2025 12:49:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2740499299101,1cyclictest151rcu_preempt11:25:1515
2740499299101,1cyclictest151rcu_preempt11:25:1415
2482912680,260ptp4l0-21swapper/107:09:231
2482912680,260ptp4l0-21swapper/107:09:231
27329991832,137cyclictest0-21swapper/409:10:2226
27329991675,160cyclictest0-21swapper/411:30:2126
27329991675,160cyclictest0-21swapper/411:30:2126
27329991672,164cyclictest0-21swapper/408:40:1626
274279916615,105cyclictest0-21swapper/2710:28:5620
27329991610,146cyclictest0-21swapper/409:15:3826
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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