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2025-03-21 - 21:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Fri Mar 21, 2025 12:50:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123669928523,64cyclictest151rcu_preempt12:13:1410
2482912070,199ptp4l0-21swapper/107:07:551
123919918623,126cyclictest0-21swapper/2109:13:4314
123919918623,126cyclictest0-21swapper/2109:13:4314
122839918148,71cyclictest0-21swapper/809:40:0130
122839918148,71cyclictest0-21swapper/809:40:0130
123919917722,98cyclictest0-21swapper/2110:51:5814
123919917121,101cyclictest28621-21timerwakeupswit08:10:2714
123919917022,89cyclictest0-21swapper/2110:56:5114
123919917022,89cyclictest0-21swapper/2110:56:5114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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